* [PATCH v3 1/6] staging: ccree: fix hash import/export
2017-06-25 7:47 [PATCH v3 0/6] staging: ccree: bug fixes and TODO items for 4.13 Gilad Ben-Yossef
@ 2017-06-25 7:47 ` Gilad Ben-Yossef
2017-06-25 7:47 ` [PATCH v3 2/6] staging: ccree: register setkey for none hash macs Gilad Ben-Yossef
` (4 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Gilad Ben-Yossef @ 2017-06-25 7:47 UTC (permalink / raw)
To: Greg Kroah-Hartman, linux-kernel, linux-crypto, driverdev-devel,
devel
Cc: Ofir Drang, Dan Carpenter
Hash import and export was saving and restoring the wrong context
and therefore disabled. Fix it by restoring intermediate digest
and additional state needed.
The hash and mac transform now pass testmgr partial hash tests.
Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
---
drivers/staging/ccree/ssi_hash.c | 143 +++++++++++++++++++++++++++------------
drivers/staging/ccree/ssi_hash.h | 2 +
2 files changed, 101 insertions(+), 44 deletions(-)
diff --git a/drivers/staging/ccree/ssi_hash.c b/drivers/staging/ccree/ssi_hash.c
index ed1c672..ffe8e1a 100644
--- a/drivers/staging/ccree/ssi_hash.c
+++ b/drivers/staging/ccree/ssi_hash.c
@@ -976,22 +976,6 @@ static int ssi_hash_init(struct ahash_req_ctx *state, struct ssi_hash_ctx *ctx)
return 0;
}
-#ifdef EXPORT_FIXED
-static int ssi_hash_export(struct ssi_hash_ctx *ctx, void *out)
-{
- CHECK_AND_RETURN_UPON_FIPS_ERROR();
- memcpy(out, ctx, sizeof(struct ssi_hash_ctx));
- return 0;
-}
-
-static int ssi_hash_import(struct ssi_hash_ctx *ctx, const void *in)
-{
- CHECK_AND_RETURN_UPON_FIPS_ERROR();
- memcpy(ctx, in, sizeof(struct ssi_hash_ctx));
- return 0;
-}
-#endif
-
static int ssi_hash_setkey(void *hash,
const u8 *key,
unsigned int keylen,
@@ -1782,23 +1766,107 @@ static int ssi_ahash_init(struct ahash_request *req)
return ssi_hash_init(state, ctx);
}
-#ifdef EXPORT_FIXED
static int ssi_ahash_export(struct ahash_request *req, void *out)
{
struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
struct ssi_hash_ctx *ctx = crypto_ahash_ctx(ahash);
+ struct device *dev = &ctx->drvdata->plat_dev->dev;
+ struct ahash_req_ctx *state = ahash_request_ctx(req);
+ u8 *curr_buff = state->buff_index ? state->buff1 : state->buff0;
+ u32 curr_buff_cnt = state->buff_index ? state->buff1_cnt :
+ state->buff0_cnt;
+ const u32 tmp = CC_EXPORT_MAGIC;
+
+ CHECK_AND_RETURN_UPON_FIPS_ERROR();
- return ssi_hash_export(ctx, out);
+ memcpy(out, &tmp, sizeof(u32));
+ out += sizeof(u32);
+
+ dma_sync_single_for_cpu(dev, state->digest_buff_dma_addr,
+ ctx->inter_digestsize, DMA_BIDIRECTIONAL);
+ memcpy(out, state->digest_buff, ctx->inter_digestsize);
+ out += ctx->inter_digestsize;
+
+ if (state->digest_bytes_len_dma_addr) {
+ dma_sync_single_for_cpu(dev, state->digest_bytes_len_dma_addr,
+ HASH_LEN_SIZE, DMA_BIDIRECTIONAL);
+ memcpy(out, state->digest_bytes_len, HASH_LEN_SIZE);
+ } else {
+ /* Poison the unused exported digest len field. */
+ memset(out, 0x5F, HASH_LEN_SIZE);
+ }
+ out += HASH_LEN_SIZE;
+
+ memcpy(out, &curr_buff_cnt, sizeof(u32));
+ out += sizeof(u32);
+
+ memcpy(out, curr_buff, curr_buff_cnt);
+
+ /* No sync for device ineeded since we did not change the data,
+ * we only copy it
+ */
+
+ return 0;
}
static int ssi_ahash_import(struct ahash_request *req, const void *in)
{
struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
struct ssi_hash_ctx *ctx = crypto_ahash_ctx(ahash);
+ struct device *dev = &ctx->drvdata->plat_dev->dev;
+ struct ahash_req_ctx *state = ahash_request_ctx(req);
+ u32 tmp;
+ int rc;
+
+ CHECK_AND_RETURN_UPON_FIPS_ERROR();
- return ssi_hash_import(ctx, in);
+ memcpy(&tmp, in, sizeof(u32));
+ if (tmp != CC_EXPORT_MAGIC) {
+ rc = -EINVAL;
+ goto out;
+ }
+ in += sizeof(u32);
+
+ rc = ssi_hash_init(state, ctx);
+ if (rc)
+ goto out;
+
+ dma_sync_single_for_cpu(dev, state->digest_buff_dma_addr,
+ ctx->inter_digestsize, DMA_BIDIRECTIONAL);
+ memcpy(state->digest_buff, in, ctx->inter_digestsize);
+ in += ctx->inter_digestsize;
+
+ if (state->digest_bytes_len_dma_addr) {
+ dma_sync_single_for_cpu(dev, state->digest_bytes_len_dma_addr,
+ HASH_LEN_SIZE, DMA_BIDIRECTIONAL);
+ memcpy(state->digest_bytes_len, in, HASH_LEN_SIZE);
+ }
+ in += HASH_LEN_SIZE;
+
+ dma_sync_single_for_device(dev, state->digest_buff_dma_addr,
+ ctx->inter_digestsize, DMA_BIDIRECTIONAL);
+
+ if (state->digest_bytes_len_dma_addr)
+ dma_sync_single_for_device(dev,
+ state->digest_bytes_len_dma_addr,
+ HASH_LEN_SIZE, DMA_BIDIRECTIONAL);
+
+ state->buff_index = 0;
+
+ /* Sanity check the data as much as possible */
+ memcpy(&tmp, in, sizeof(u32));
+ if (tmp > SSI_MAX_HASH_BLCK_SIZE) {
+ rc = -EINVAL;
+ goto out;
+ }
+ in += sizeof(u32);
+
+ state->buff0_cnt = tmp;
+ memcpy(state->buff0, in, state->buff0_cnt);
+
+out:
+ return rc;
}
-#endif
static int ssi_ahash_setkey(struct crypto_ahash *ahash,
const u8 *key, unsigned int keylen)
@@ -1820,6 +1888,9 @@ struct ssi_hash_template {
struct ssi_drvdata *drvdata;
};
+#define CC_STATE_SIZE(_x) \
+ ((_x) + HASH_LEN_SIZE + SSI_MAX_HASH_BLCK_SIZE + (2 * sizeof(u32)))
+
/* hash descriptors */
static struct ssi_hash_template driver_hash[] = {
//Asynchronize hash template
@@ -1836,14 +1907,12 @@ static struct ssi_hash_template driver_hash[] = {
.final = ssi_ahash_final,
.finup = ssi_ahash_finup,
.digest = ssi_ahash_digest,
-#ifdef EXPORT_FIXED
.export = ssi_ahash_export,
.import = ssi_ahash_import,
-#endif
.setkey = ssi_ahash_setkey,
.halg = {
.digestsize = SHA1_DIGEST_SIZE,
- .statesize = sizeof(struct sha1_state),
+ .statesize = CC_STATE_SIZE(SHA1_DIGEST_SIZE),
},
},
.hash_mode = DRV_HASH_SHA1,
@@ -1862,14 +1931,12 @@ static struct ssi_hash_template driver_hash[] = {
.final = ssi_ahash_final,
.finup = ssi_ahash_finup,
.digest = ssi_ahash_digest,
-#ifdef EXPORT_FIXED
.export = ssi_ahash_export,
.import = ssi_ahash_import,
-#endif
.setkey = ssi_ahash_setkey,
.halg = {
.digestsize = SHA256_DIGEST_SIZE,
- .statesize = sizeof(struct sha256_state),
+ .statesize = CC_STATE_SIZE(SHA256_DIGEST_SIZE)
},
},
.hash_mode = DRV_HASH_SHA256,
@@ -1888,14 +1955,12 @@ static struct ssi_hash_template driver_hash[] = {
.final = ssi_ahash_final,
.finup = ssi_ahash_finup,
.digest = ssi_ahash_digest,
-#ifdef EXPORT_FIXED
.export = ssi_ahash_export,
.import = ssi_ahash_import,
-#endif
.setkey = ssi_ahash_setkey,
.halg = {
.digestsize = SHA224_DIGEST_SIZE,
- .statesize = sizeof(struct sha256_state),
+ .statesize = CC_STATE_SIZE(SHA224_DIGEST_SIZE),
},
},
.hash_mode = DRV_HASH_SHA224,
@@ -1915,14 +1980,12 @@ static struct ssi_hash_template driver_hash[] = {
.final = ssi_ahash_final,
.finup = ssi_ahash_finup,
.digest = ssi_ahash_digest,
-#ifdef EXPORT_FIXED
.export = ssi_ahash_export,
.import = ssi_ahash_import,
-#endif
.setkey = ssi_ahash_setkey,
.halg = {
.digestsize = SHA384_DIGEST_SIZE,
- .statesize = sizeof(struct sha512_state),
+ .statesize = CC_STATE_SIZE(SHA384_DIGEST_SIZE),
},
},
.hash_mode = DRV_HASH_SHA384,
@@ -1941,14 +2004,12 @@ static struct ssi_hash_template driver_hash[] = {
.final = ssi_ahash_final,
.finup = ssi_ahash_finup,
.digest = ssi_ahash_digest,
-#ifdef EXPORT_FIXED
.export = ssi_ahash_export,
.import = ssi_ahash_import,
-#endif
.setkey = ssi_ahash_setkey,
.halg = {
.digestsize = SHA512_DIGEST_SIZE,
- .statesize = sizeof(struct sha512_state),
+ .statesize = CC_STATE_SIZE(SHA512_DIGEST_SIZE),
},
},
.hash_mode = DRV_HASH_SHA512,
@@ -1968,14 +2029,12 @@ static struct ssi_hash_template driver_hash[] = {
.final = ssi_ahash_final,
.finup = ssi_ahash_finup,
.digest = ssi_ahash_digest,
-#ifdef EXPORT_FIXED
.export = ssi_ahash_export,
.import = ssi_ahash_import,
-#endif
.setkey = ssi_ahash_setkey,
.halg = {
.digestsize = MD5_DIGEST_SIZE,
- .statesize = sizeof(struct md5_state),
+ .statesize = CC_STATE_SIZE(MD5_DIGEST_SIZE),
},
},
.hash_mode = DRV_HASH_MD5,
@@ -1993,13 +2052,11 @@ static struct ssi_hash_template driver_hash[] = {
.finup = ssi_mac_finup,
.digest = ssi_mac_digest,
.setkey = ssi_xcbc_setkey,
-#ifdef EXPORT_FIXED
.export = ssi_ahash_export,
.import = ssi_ahash_import,
-#endif
.halg = {
.digestsize = AES_BLOCK_SIZE,
- .statesize = sizeof(struct aeshash_state),
+ .statesize = CC_STATE_SIZE(AES_BLOCK_SIZE),
},
},
.hash_mode = DRV_HASH_NULL,
@@ -2018,13 +2075,11 @@ static struct ssi_hash_template driver_hash[] = {
.finup = ssi_mac_finup,
.digest = ssi_mac_digest,
.setkey = ssi_cmac_setkey,
-#ifdef EXPORT_FIXED
.export = ssi_ahash_export,
.import = ssi_ahash_import,
-#endif
.halg = {
.digestsize = AES_BLOCK_SIZE,
- .statesize = sizeof(struct aeshash_state),
+ .statesize = CC_STATE_SIZE(AES_BLOCK_SIZE),
},
},
.hash_mode = DRV_HASH_NULL,
diff --git a/drivers/staging/ccree/ssi_hash.h b/drivers/staging/ccree/ssi_hash.h
index 7c94661..0bb99cb 100644
--- a/drivers/staging/ccree/ssi_hash.h
+++ b/drivers/staging/ccree/ssi_hash.h
@@ -39,6 +39,8 @@
#define XCBC_MAC_K2_OFFSET 16
#define XCBC_MAC_K3_OFFSET 32
+#define CC_EXPORT_MAGIC 0xC2EE1070U
+
// this struct was taken from drivers/crypto/nx/nx-aes-xcbc.c and it is used for xcbc/cmac statesize
struct aeshash_state {
u8 state[AES_BLOCK_SIZE];
--
2.1.4
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v3 2/6] staging: ccree: register setkey for none hash macs
2017-06-25 7:47 [PATCH v3 0/6] staging: ccree: bug fixes and TODO items for 4.13 Gilad Ben-Yossef
2017-06-25 7:47 ` [PATCH v3 1/6] staging: ccree: fix hash import/export Gilad Ben-Yossef
@ 2017-06-25 7:47 ` Gilad Ben-Yossef
2017-06-25 7:47 ` [PATCH v3 3/6] staging: ccree: remove unused function Gilad Ben-Yossef
` (3 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Gilad Ben-Yossef @ 2017-06-25 7:47 UTC (permalink / raw)
To: Greg Kroah-Hartman, linux-kernel, linux-crypto, driverdev-devel,
devel
Cc: Dan Carpenter, Ofir Drang
The original ccree driver was registering a useless setkey
method even for non-MAC hash transformations. Somewhere
around v4.9 a check was added that failed hash operations
if a setkey method was registered but was not called,
so during the initial upstream port code was added to
only register the setkey method for MAC type hash transform.
Unfortunately, the ccree driver also registers non-hash based
MAC transforms and the code had a logic error that stopped
it registering a setkey callback even for those, thus rendering
them useless.
This commit fixes the logic mistake, thus correctly registering
a setkey method only for MAC transformations, leaving it out
for non-MAC ones, whether they are hash based on not.
Fixes: 50cfbbb7e627 ("staging: ccree: add ahash support").
Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
---
drivers/staging/ccree/ssi_hash.c | 83 ++++++++++++++++++++--------------------
1 file changed, 42 insertions(+), 41 deletions(-)
diff --git a/drivers/staging/ccree/ssi_hash.c b/drivers/staging/ccree/ssi_hash.c
index ffe8e1a..bfe2bec 100644
--- a/drivers/staging/ccree/ssi_hash.c
+++ b/drivers/staging/ccree/ssi_hash.c
@@ -1877,8 +1877,8 @@ static int ssi_ahash_setkey(struct crypto_ahash *ahash,
struct ssi_hash_template {
char name[CRYPTO_MAX_ALG_NAME];
char driver_name[CRYPTO_MAX_ALG_NAME];
- char hmac_name[CRYPTO_MAX_ALG_NAME];
- char hmac_driver_name[CRYPTO_MAX_ALG_NAME];
+ char mac_name[CRYPTO_MAX_ALG_NAME];
+ char mac_driver_name[CRYPTO_MAX_ALG_NAME];
unsigned int blocksize;
bool synchronize;
struct ahash_alg template_ahash;
@@ -1897,8 +1897,8 @@ static struct ssi_hash_template driver_hash[] = {
{
.name = "sha1",
.driver_name = "sha1-dx",
- .hmac_name = "hmac(sha1)",
- .hmac_driver_name = "hmac-sha1-dx",
+ .mac_name = "hmac(sha1)",
+ .mac_driver_name = "hmac-sha1-dx",
.blocksize = SHA1_BLOCK_SIZE,
.synchronize = false,
.template_ahash = {
@@ -1922,8 +1922,8 @@ static struct ssi_hash_template driver_hash[] = {
{
.name = "sha256",
.driver_name = "sha256-dx",
- .hmac_name = "hmac(sha256)",
- .hmac_driver_name = "hmac-sha256-dx",
+ .mac_name = "hmac(sha256)",
+ .mac_driver_name = "hmac-sha256-dx",
.blocksize = SHA256_BLOCK_SIZE,
.template_ahash = {
.init = ssi_ahash_init,
@@ -1946,8 +1946,8 @@ static struct ssi_hash_template driver_hash[] = {
{
.name = "sha224",
.driver_name = "sha224-dx",
- .hmac_name = "hmac(sha224)",
- .hmac_driver_name = "hmac-sha224-dx",
+ .mac_name = "hmac(sha224)",
+ .mac_driver_name = "hmac-sha224-dx",
.blocksize = SHA224_BLOCK_SIZE,
.template_ahash = {
.init = ssi_ahash_init,
@@ -1971,8 +1971,8 @@ static struct ssi_hash_template driver_hash[] = {
{
.name = "sha384",
.driver_name = "sha384-dx",
- .hmac_name = "hmac(sha384)",
- .hmac_driver_name = "hmac-sha384-dx",
+ .mac_name = "hmac(sha384)",
+ .mac_driver_name = "hmac-sha384-dx",
.blocksize = SHA384_BLOCK_SIZE,
.template_ahash = {
.init = ssi_ahash_init,
@@ -1995,8 +1995,8 @@ static struct ssi_hash_template driver_hash[] = {
{
.name = "sha512",
.driver_name = "sha512-dx",
- .hmac_name = "hmac(sha512)",
- .hmac_driver_name = "hmac-sha512-dx",
+ .mac_name = "hmac(sha512)",
+ .mac_driver_name = "hmac-sha512-dx",
.blocksize = SHA512_BLOCK_SIZE,
.template_ahash = {
.init = ssi_ahash_init,
@@ -2020,8 +2020,8 @@ static struct ssi_hash_template driver_hash[] = {
{
.name = "md5",
.driver_name = "md5-dx",
- .hmac_name = "hmac(md5)",
- .hmac_driver_name = "hmac-md5-dx",
+ .mac_name = "hmac(md5)",
+ .mac_driver_name = "hmac-md5-dx",
.blocksize = MD5_HMAC_BLOCK_SIZE,
.template_ahash = {
.init = ssi_ahash_init,
@@ -2042,8 +2042,8 @@ static struct ssi_hash_template driver_hash[] = {
.inter_digestsize = MD5_DIGEST_SIZE,
},
{
- .name = "xcbc(aes)",
- .driver_name = "xcbc-aes-dx",
+ .mac_name = "xcbc(aes)",
+ .mac_driver_name = "xcbc-aes-dx",
.blocksize = AES_BLOCK_SIZE,
.template_ahash = {
.init = ssi_ahash_init,
@@ -2065,8 +2065,8 @@ static struct ssi_hash_template driver_hash[] = {
},
#if SSI_CC_HAS_CMAC
{
- .name = "cmac(aes)",
- .driver_name = "cmac-aes-dx",
+ .mac_name = "cmac(aes)",
+ .mac_driver_name = "cmac-aes-dx",
.blocksize = AES_BLOCK_SIZE,
.template_ahash = {
.init = ssi_ahash_init,
@@ -2109,9 +2109,9 @@ ssi_hash_create_alg(struct ssi_hash_template *template, bool keyed)
if (keyed) {
snprintf(alg->cra_name, CRYPTO_MAX_ALG_NAME, "%s",
- template->hmac_name);
+ template->mac_name);
snprintf(alg->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",
- template->hmac_driver_name);
+ template->mac_driver_name);
} else {
halg->setkey = NULL;
snprintf(alg->cra_name, CRYPTO_MAX_ALG_NAME, "%s",
@@ -2300,32 +2300,33 @@ int ssi_hash_alloc(struct ssi_drvdata *drvdata)
/* ahash registration */
for (alg = 0; alg < ARRAY_SIZE(driver_hash); alg++) {
struct ssi_hash_alg *t_alg;
+ int hw_mode = driver_hash[alg].hw_mode;
/* register hmac version */
+ t_alg = ssi_hash_create_alg(&driver_hash[alg], true);
+ if (IS_ERR(t_alg)) {
+ rc = PTR_ERR(t_alg);
+ SSI_LOG_ERR("%s alg allocation failed\n",
+ driver_hash[alg].driver_name);
+ goto fail;
+ }
+ t_alg->drvdata = drvdata;
- if ((((struct ssi_hash_template *)&driver_hash[alg])->hw_mode != DRV_CIPHER_XCBC_MAC) &&
- (((struct ssi_hash_template *)&driver_hash[alg])->hw_mode != DRV_CIPHER_CMAC)) {
- t_alg = ssi_hash_create_alg(&driver_hash[alg], true);
- if (IS_ERR(t_alg)) {
- rc = PTR_ERR(t_alg);
- SSI_LOG_ERR("%s alg allocation failed\n",
- driver_hash[alg].driver_name);
- goto fail;
- }
- t_alg->drvdata = drvdata;
-
- rc = crypto_register_ahash(&t_alg->ahash_alg);
- if (unlikely(rc)) {
- SSI_LOG_ERR("%s alg registration failed\n",
- driver_hash[alg].driver_name);
- kfree(t_alg);
- goto fail;
- } else {
- list_add_tail(&t_alg->entry,
- &hash_handle->hash_list);
- }
+ rc = crypto_register_ahash(&t_alg->ahash_alg);
+ if (unlikely(rc)) {
+ SSI_LOG_ERR("%s alg registration failed\n",
+ driver_hash[alg].driver_name);
+ kfree(t_alg);
+ goto fail;
+ } else {
+ list_add_tail(&t_alg->entry,
+ &hash_handle->hash_list);
}
+ if ((hw_mode == DRV_CIPHER_XCBC_MAC) ||
+ (hw_mode == DRV_CIPHER_CMAC))
+ continue;
+
/* register hash version */
t_alg = ssi_hash_create_alg(&driver_hash[alg], false);
if (IS_ERR(t_alg)) {
--
2.1.4
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v3 3/6] staging: ccree: remove unused function
2017-06-25 7:47 [PATCH v3 0/6] staging: ccree: bug fixes and TODO items for 4.13 Gilad Ben-Yossef
2017-06-25 7:47 ` [PATCH v3 1/6] staging: ccree: fix hash import/export Gilad Ben-Yossef
2017-06-25 7:47 ` [PATCH v3 2/6] staging: ccree: register setkey for none hash macs Gilad Ben-Yossef
@ 2017-06-25 7:47 ` Gilad Ben-Yossef
2017-06-25 7:47 ` [PATCH v3 4/6] staging: ccree: add clock management support Gilad Ben-Yossef
` (2 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Gilad Ben-Yossef @ 2017-06-25 7:47 UTC (permalink / raw)
To: Greg Kroah-Hartman, linux-kernel, linux-crypto, driverdev-devel,
devel
Cc: Dan Carpenter, Ofir Drang
The function set_ack_last was not used anywhere. Remove it.
Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
---
drivers/staging/ccree/cc_hw_queue_defs.h | 12 ------------
1 file changed, 12 deletions(-)
diff --git a/drivers/staging/ccree/cc_hw_queue_defs.h b/drivers/staging/ccree/cc_hw_queue_defs.h
index aaa56c8..f11487a 100644
--- a/drivers/staging/ccree/cc_hw_queue_defs.h
+++ b/drivers/staging/ccree/cc_hw_queue_defs.h
@@ -226,18 +226,6 @@ static inline void set_queue_last_ind(struct cc_hw_desc *pdesc)
}
/*
- * Signs the end of HW descriptors flow by asking for completion ack,
- * and release the HW engines
- *
- * @pdesc: pointer HW descriptor struct
- */
-static inline void set_ack_last(struct cc_hw_desc *pdesc)
-{
- pdesc->word[3] |= FIELD_PREP(WORD3_QUEUE_LAST_IND, 1);
- pdesc->word[4] |= FIELD_PREP(WORD4_ACK_NEEDED, 1);
-}
-
-/*
* Set the DIN field of a HW descriptors
*
* @pdesc: pointer HW descriptor struct
--
2.1.4
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v3 4/6] staging: ccree: add clock management support
2017-06-25 7:47 [PATCH v3 0/6] staging: ccree: bug fixes and TODO items for 4.13 Gilad Ben-Yossef
` (2 preceding siblings ...)
2017-06-25 7:47 ` [PATCH v3 3/6] staging: ccree: remove unused function Gilad Ben-Yossef
@ 2017-06-25 7:47 ` Gilad Ben-Yossef
2017-06-25 7:47 ` [PATCH v3 5/6] staging: ccree: add DT bus coherency detection Gilad Ben-Yossef
2017-06-25 7:47 ` [PATCH v3 6/6] staging: ccree: use signal safe completion wait Gilad Ben-Yossef
5 siblings, 0 replies; 7+ messages in thread
From: Gilad Ben-Yossef @ 2017-06-25 7:47 UTC (permalink / raw)
To: Greg Kroah-Hartman, linux-kernel, linux-crypto, driverdev-devel,
devel
Cc: Dan Carpenter, Ofir Drang
Some SoC which implement CryptoCell have a dedicated clock
tied to it, some do not. Implement clock support if exists
based on device tree data and tie power management to it.
Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
---
drivers/staging/ccree/Makefile | 2 +-
drivers/staging/ccree/ssi_driver.c | 43 +++++++++++++++++++++++----
drivers/staging/ccree/ssi_driver.h | 5 +++-
drivers/staging/ccree/ssi_pm.c | 13 +++++----
drivers/staging/ccree/ssi_pm_ext.c | 60 --------------------------------------
drivers/staging/ccree/ssi_pm_ext.h | 33 ---------------------
6 files changed, 50 insertions(+), 106 deletions(-)
delete mode 100644 drivers/staging/ccree/ssi_pm_ext.c
delete mode 100644 drivers/staging/ccree/ssi_pm_ext.h
diff --git a/drivers/staging/ccree/Makefile b/drivers/staging/ccree/Makefile
index 44f3e3e..318c2b3 100644
--- a/drivers/staging/ccree/Makefile
+++ b/drivers/staging/ccree/Makefile
@@ -1,3 +1,3 @@
obj-$(CONFIG_CRYPTO_DEV_CCREE) := ccree.o
-ccree-y := ssi_driver.o ssi_sysfs.o ssi_buffer_mgr.o ssi_request_mgr.o ssi_cipher.o ssi_hash.o ssi_aead.o ssi_ivgen.o ssi_sram_mgr.o ssi_pm.o ssi_pm_ext.o
+ccree-y := ssi_driver.o ssi_sysfs.o ssi_buffer_mgr.o ssi_request_mgr.o ssi_cipher.o ssi_hash.o ssi_aead.o ssi_ivgen.o ssi_sram_mgr.o ssi_pm.o
ccree-$(CCREE_FIPS_SUPPORT) += ssi_fips.o ssi_fips_ll.o ssi_fips_ext.o ssi_fips_local.o
diff --git a/drivers/staging/ccree/ssi_driver.c b/drivers/staging/ccree/ssi_driver.c
index b9d0dd27..c516675 100644
--- a/drivers/staging/ccree/ssi_driver.c
+++ b/drivers/staging/ccree/ssi_driver.c
@@ -57,6 +57,7 @@
#include <linux/sched.h>
#include <linux/random.h>
#include <linux/of.h>
+#include <linux/clk.h>
#include "ssi_config.h"
#include "ssi_driver.h"
@@ -219,6 +220,8 @@ static int init_cc_resources(struct platform_device *plat_dev)
void __iomem *cc_base = NULL;
bool irq_registered = false;
struct ssi_drvdata *new_drvdata = kzalloc(sizeof(struct ssi_drvdata), GFP_KERNEL);
+ struct device *dev = &plat_dev->dev;
+ struct device_node *np = dev->of_node;
u32 signature_val;
int rc = 0;
@@ -228,6 +231,8 @@ static int init_cc_resources(struct platform_device *plat_dev)
goto init_cc_res_err;
}
+ new_drvdata->clk = of_clk_get(np, 0);
+
/*Initialize inflight counter used in dx_ablkcipher_secure_complete used for count of BYSPASS blocks operations*/
new_drvdata->inflight_counter = 0;
@@ -286,6 +291,10 @@ static int init_cc_resources(struct platform_device *plat_dev)
new_drvdata->plat_dev = plat_dev;
+ rc = cc_clk_on(new_drvdata);
+ if (rc)
+ goto init_cc_res_err;
+
if(new_drvdata->plat_dev->dev.dma_mask == NULL)
{
new_drvdata->plat_dev->dev.dma_mask = & new_drvdata->plat_dev->dev.coherent_dma_mask;
@@ -450,14 +459,11 @@ static void cleanup_cc_resources(struct platform_device *plat_dev)
ssi_sysfs_fini();
#endif
- /* Mask all interrupts */
- WRITE_REGISTER(drvdata->cc_base + CC_REG_OFFSET(HOST_RGF, HOST_IMR),
- 0xFFFFFFFF);
+ fini_cc_regs(drvdata);
+ cc_clk_off(drvdata);
free_irq(drvdata->res_irq->start, drvdata);
drvdata->res_irq = NULL;
- fini_cc_regs(drvdata);
-
if (drvdata->cc_base != NULL) {
iounmap(drvdata->cc_base);
release_mem_region(drvdata->res_mem->start,
@@ -470,6 +476,33 @@ static void cleanup_cc_resources(struct platform_device *plat_dev)
dev_set_drvdata(&plat_dev->dev, NULL);
}
+int cc_clk_on(struct ssi_drvdata *drvdata)
+{
+ struct clk *clk = drvdata->clk;
+ int rc;
+
+ if (IS_ERR(clk))
+ /* Not all devices have a clock associated with CCREE */
+ return 0;
+
+ rc = clk_prepare_enable(clk);
+ if (rc)
+ return rc;
+
+ return 0;
+}
+
+void cc_clk_off(struct ssi_drvdata *drvdata)
+{
+ struct clk *clk = drvdata->clk;
+
+ if (IS_ERR(clk))
+ /* Not all devices have a clock associated with CCREE */
+ return;
+
+ clk_disable_unprepare(clk);
+}
+
static int cc7x_probe(struct platform_device *plat_dev)
{
int rc;
diff --git a/drivers/staging/ccree/ssi_driver.h b/drivers/staging/ccree/ssi_driver.h
index 78a327a..faf47b1 100644
--- a/drivers/staging/ccree/ssi_driver.h
+++ b/drivers/staging/ccree/ssi_driver.h
@@ -36,6 +36,7 @@
#include <crypto/authenc.h>
#include <crypto/hash.h>
#include <linux/version.h>
+#include <linux/clk.h>
/* Registers definitions from shared/hw/ree_include */
#include "dx_reg_base_host.h"
@@ -148,7 +149,7 @@ struct ssi_drvdata {
void *ivgen_handle;
void *sram_mgr_handle;
u32 inflight_counter;
-
+ struct clk *clk;
};
struct ssi_crypto_alg {
@@ -193,6 +194,8 @@ void dump_byte_array(const char *name, const u8 *the_array, unsigned long size);
int init_cc_regs(struct ssi_drvdata *drvdata, bool is_probe);
void fini_cc_regs(struct ssi_drvdata *drvdata);
+int cc_clk_on(struct ssi_drvdata *drvdata);
+void cc_clk_off(struct ssi_drvdata *drvdata);
#endif /*__SSI_DRIVER_H__*/
diff --git a/drivers/staging/ccree/ssi_pm.c b/drivers/staging/ccree/ssi_pm.c
index 5bfbdd0..67ae1dc 100644
--- a/drivers/staging/ccree/ssi_pm.c
+++ b/drivers/staging/ccree/ssi_pm.c
@@ -29,7 +29,6 @@
#include "ssi_ivgen.h"
#include "ssi_hash.h"
#include "ssi_pm.h"
-#include "ssi_pm_ext.h"
#if defined (CONFIG_PM_RUNTIME) || defined (CONFIG_PM_SLEEP)
@@ -52,9 +51,7 @@ int ssi_power_mgr_runtime_suspend(struct device *dev)
return rc;
}
fini_cc_regs(drvdata);
-
- /* Specific HW suspend code */
- ssi_pm_ext_hw_suspend(dev);
+ cc_clk_off(drvdata);
return 0;
}
@@ -66,8 +63,12 @@ int ssi_power_mgr_runtime_resume(struct device *dev)
SSI_LOG_DEBUG("ssi_power_mgr_runtime_resume , unset HOST_POWER_DOWN_EN\n");
WRITE_REGISTER(drvdata->cc_base + CC_REG_OFFSET(HOST_RGF, HOST_POWER_DOWN_EN), POWER_DOWN_DISABLE);
- /* Specific HW resume code */
- ssi_pm_ext_hw_resume(dev);
+
+ rc = cc_clk_on(drvdata);
+ if (rc) {
+ SSI_LOG_ERR("failed getting clock back on. We're toast.\n");
+ return rc;
+ }
rc = init_cc_regs(drvdata, false);
if (rc !=0) {
diff --git a/drivers/staging/ccree/ssi_pm_ext.c b/drivers/staging/ccree/ssi_pm_ext.c
deleted file mode 100644
index 453151c..0000000
--- a/drivers/staging/ccree/ssi_pm_ext.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Copyright (C) 2012-2017 ARM Limited or its affiliates.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see <http://www.gnu.org/licenses/>.
- */
-
-
-#include "ssi_config.h"
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/interrupt.h>
-#include <crypto/ctr.h>
-#include <linux/pm_runtime.h>
-#include "ssi_driver.h"
-#include "ssi_sram_mgr.h"
-#include "ssi_pm_ext.h"
-
-/*
- * This function should suspend the HW (if possiable), It should be implemented by
- * the driver user.
- * The reference code clears the internal SRAM to imitate lose of state.
- */
-void ssi_pm_ext_hw_suspend(struct device *dev)
-{
- struct ssi_drvdata *drvdata =
- (struct ssi_drvdata *)dev_get_drvdata(dev);
- unsigned int val;
- void __iomem *cc_base = drvdata->cc_base;
- unsigned int sram_addr = 0;
-
- CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, SRAM_ADDR), sram_addr);
-
- for (;sram_addr < SSI_CC_SRAM_SIZE ; sram_addr+=4) {
- CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, SRAM_DATA), 0x0);
-
- do {
- val = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, SRAM_DATA_READY));
- } while (!(val &0x1));
- }
-}
-
-/*
- * This function should resume the HW (if possiable).It should be implemented by
- * the driver user.
- */
-void ssi_pm_ext_hw_resume(struct device *dev)
-{
- return;
-}
-
diff --git a/drivers/staging/ccree/ssi_pm_ext.h b/drivers/staging/ccree/ssi_pm_ext.h
deleted file mode 100644
index dbe658b..0000000
--- a/drivers/staging/ccree/ssi_pm_ext.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright (C) 2012-2017 ARM Limited or its affiliates.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see <http://www.gnu.org/licenses/>.
- */
-
-/* \file ssi_pm_ext.h
- */
-
-#ifndef __PM_EXT_H__
-#define __PM_EXT_H__
-
-
-#include "ssi_config.h"
-#include "ssi_driver.h"
-
-void ssi_pm_ext_hw_suspend(struct device *dev);
-
-void ssi_pm_ext_hw_resume(struct device *dev);
-
-
-#endif /*__POWER_MGR_H__*/
-
--
2.1.4
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v3 5/6] staging: ccree: add DT bus coherency detection
2017-06-25 7:47 [PATCH v3 0/6] staging: ccree: bug fixes and TODO items for 4.13 Gilad Ben-Yossef
` (3 preceding siblings ...)
2017-06-25 7:47 ` [PATCH v3 4/6] staging: ccree: add clock management support Gilad Ben-Yossef
@ 2017-06-25 7:47 ` Gilad Ben-Yossef
2017-06-25 7:47 ` [PATCH v3 6/6] staging: ccree: use signal safe completion wait Gilad Ben-Yossef
5 siblings, 0 replies; 7+ messages in thread
From: Gilad Ben-Yossef @ 2017-06-25 7:47 UTC (permalink / raw)
To: Greg Kroah-Hartman, linux-kernel, linux-crypto, driverdev-devel,
devel
Cc: Ofir Drang, Dan Carpenter
The ccree driver has build time configurable support
to work on top of coherent (e.g. ACP) vs. none coherent bus
connections. Turn it to run-time configurable option
based on device tree.
Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
---
drivers/staging/ccree/Kconfig | 9 ---------
drivers/staging/ccree/ssi_buffer_mgr.c | 37 ++++++++++++++++++----------------
drivers/staging/ccree/ssi_config.h | 20 ------------------
drivers/staging/ccree/ssi_driver.c | 12 ++++++++---
drivers/staging/ccree/ssi_driver.h | 3 +++
5 files changed, 32 insertions(+), 49 deletions(-)
diff --git a/drivers/staging/ccree/Kconfig b/drivers/staging/ccree/Kconfig
index 4be87f5..ec3749d 100644
--- a/drivers/staging/ccree/Kconfig
+++ b/drivers/staging/ccree/Kconfig
@@ -32,12 +32,3 @@ config CCREE_FIPS_SUPPORT
Say 'Y' to enable support for FIPS compliant mode by the
CCREE driver.
If unsure say N.
-
-config CCREE_DISABLE_COHERENT_DMA_OPS
- bool "Disable Coherent DMA operations for the CCREE driver"
- depends on CRYPTO_DEV_CCREE
- default n
- help
- Say 'Y' to disable the use of coherent DMA operations by the
- CCREE driver for debugging purposes.
- If unsure say N.
diff --git a/drivers/staging/ccree/ssi_buffer_mgr.c b/drivers/staging/ccree/ssi_buffer_mgr.c
index 88ebda8..4373d1d 100644
--- a/drivers/staging/ccree/ssi_buffer_mgr.c
+++ b/drivers/staging/ccree/ssi_buffer_mgr.c
@@ -627,6 +627,7 @@ void ssi_buffer_mgr_unmap_aead_request(
struct aead_req_ctx *areq_ctx = aead_request_ctx(req);
unsigned int hw_iv_size = areq_ctx->hw_iv_size;
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
+ struct ssi_drvdata *drvdata = dev_get_drvdata(dev);
u32 dummy;
bool chained;
u32 size_to_unmap = 0;
@@ -700,8 +701,8 @@ void ssi_buffer_mgr_unmap_aead_request(
dma_unmap_sg(dev, req->dst, ssi_buffer_mgr_get_sgl_nents(req->dst,size_to_unmap,&dummy,&chained),
DMA_BIDIRECTIONAL);
}
-#if DX_HAS_ACP
- if ((areq_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_DECRYPT) &&
+ if (drvdata->coherent &&
+ (areq_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_DECRYPT) &&
likely(req->src == req->dst))
{
u32 size_to_skip = req->assoclen;
@@ -716,7 +717,6 @@ void ssi_buffer_mgr_unmap_aead_request(
size_to_skip+ req->cryptlen - areq_ctx->req_authsize,
size_to_skip+ req->cryptlen, SSI_SG_FROM_BUF);
}
-#endif
}
static inline int ssi_buffer_mgr_get_aead_icv_nents(
@@ -981,20 +981,24 @@ static inline int ssi_buffer_mgr_prepare_aead_data_mlli(
* MAC verification upon request completion
*/
if (direct == DRV_CRYPTO_DIRECTION_DECRYPT) {
-#if !DX_HAS_ACP
- /* In ACP platform we already copying ICV
- * for any INPLACE-DECRYPT operation, hence
+ if (!drvdata->coherent) {
+ /* In coherent platforms (e.g. ACP)
+ * already copying ICV for any
+ * INPLACE-DECRYPT operation, hence
* we must neglect this code.
*/
- u32 size_to_skip = req->assoclen;
- if (areq_ctx->is_gcm4543) {
- size_to_skip += crypto_aead_ivsize(tfm);
+ u32 skip = req->assoclen;
+
+ if (areq_ctx->is_gcm4543)
+ skip += crypto_aead_ivsize(tfm);
+
+ ssi_buffer_mgr_copy_scatterlist_portion(
+ areq_ctx->backup_mac, req->src,
+ (skip + req->cryptlen -
+ areq_ctx->req_authsize),
+ skip + req->cryptlen,
+ SSI_SG_TO_BUF);
}
- ssi_buffer_mgr_copy_scatterlist_portion(
- areq_ctx->backup_mac, req->src,
- size_to_skip+ req->cryptlen - areq_ctx->req_authsize,
- size_to_skip+ req->cryptlen, SSI_SG_TO_BUF);
-#endif
areq_ctx->icv_virt_addr = areq_ctx->backup_mac;
} else {
areq_ctx->icv_virt_addr = areq_ctx->mac_buf;
@@ -1281,8 +1285,8 @@ int ssi_buffer_mgr_map_aead_request(
mlli_params->curr_pool = NULL;
sg_data.num_of_buffers = 0;
-#if DX_HAS_ACP
- if ((areq_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_DECRYPT) &&
+ if (drvdata->coherent &&
+ (areq_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_DECRYPT) &&
likely(req->src == req->dst))
{
u32 size_to_skip = req->assoclen;
@@ -1297,7 +1301,6 @@ int ssi_buffer_mgr_map_aead_request(
size_to_skip+ req->cryptlen - areq_ctx->req_authsize,
size_to_skip+ req->cryptlen, SSI_SG_TO_BUF);
}
-#endif
/* cacluate the size for cipher remove ICV in decrypt*/
areq_ctx->cryptlen = (areq_ctx->gen_ctx.op_type ==
diff --git a/drivers/staging/ccree/ssi_config.h b/drivers/staging/ccree/ssi_config.h
index b7c0576..ff7597c 100644
--- a/drivers/staging/ccree/ssi_config.h
+++ b/drivers/staging/ccree/ssi_config.h
@@ -23,7 +23,6 @@
#include <linux/version.h>
-#define DISABLE_COHERENT_DMA_OPS
//#define FLUSH_CACHE_ALL
//#define COMPLETION_DELAY
//#define DX_DUMP_DESCS
@@ -33,24 +32,5 @@
//#define DX_IRQ_DELAY 100000
#define DMA_BIT_MASK_LEN 48 /* was 32 bit, but for juno's sake it was enlarged to 48 bit */
-#if defined (CONFIG_ARM64) // TODO currently only this mode was test on Juno (which is ARM64), need to enable coherent also.
-#define DISABLE_COHERENT_DMA_OPS
-#endif
-
-/* Define the CryptoCell DMA cache coherency signals configuration */
-#if defined (DISABLE_COHERENT_DMA_OPS)
- /* Software Controlled Cache Coherency (SCCC) */
- #define SSI_CACHE_PARAMS (0x000)
- /* CC attached to NONE-ACP such as HPP/ACE/AMBA4.
- * The customer is responsible to enable/disable this feature
- * according to his platform type.
- */
- #define DX_HAS_ACP 0
-#else
- #define SSI_CACHE_PARAMS (0xEEE)
- /* CC attached to ACP */
- #define DX_HAS_ACP 1
-#endif
-
#endif /*__DX_CONFIG_H__*/
diff --git a/drivers/staging/ccree/ssi_driver.c b/drivers/staging/ccree/ssi_driver.c
index c516675..151afcf 100644
--- a/drivers/staging/ccree/ssi_driver.c
+++ b/drivers/staging/ccree/ssi_driver.c
@@ -58,6 +58,7 @@
#include <linux/random.h>
#include <linux/of.h>
#include <linux/clk.h>
+#include <linux/of_address.h>
#include "ssi_config.h"
#include "ssi_driver.h"
@@ -172,7 +173,7 @@ static irqreturn_t cc_isr(int irq, void *dev_id)
int init_cc_regs(struct ssi_drvdata *drvdata, bool is_probe)
{
- unsigned int val;
+ unsigned int val, cache_params;
void __iomem *cc_base = drvdata->cc_base;
/* Unmask all AXI interrupt sources AXI_CFG1 register */
@@ -201,14 +202,18 @@ int init_cc_regs(struct ssi_drvdata *drvdata, bool is_probe)
}
#endif
+ cache_params = (drvdata->coherent ? CC_COHERENT_CACHE_PARAMS : 0x0);
+
val = CC_HAL_READ_REGISTER(CC_REG_OFFSET(CRY_KERNEL, AXIM_CACHE_PARAMS));
if (is_probe == true) {
SSI_LOG_INFO("Cache params previous: 0x%08X\n", val);
}
- CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(CRY_KERNEL, AXIM_CACHE_PARAMS), SSI_CACHE_PARAMS);
+ CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(CRY_KERNEL, AXIM_CACHE_PARAMS),
+ cache_params);
val = CC_HAL_READ_REGISTER(CC_REG_OFFSET(CRY_KERNEL, AXIM_CACHE_PARAMS));
if (is_probe == true) {
- SSI_LOG_INFO("Cache params current: 0x%08X (expected: 0x%08X)\n", val, SSI_CACHE_PARAMS);
+ SSI_LOG_INFO("Cache params current: 0x%08X (expect: 0x%08X)\n",
+ val, cache_params);
}
return 0;
@@ -232,6 +237,7 @@ static int init_cc_resources(struct platform_device *plat_dev)
}
new_drvdata->clk = of_clk_get(np, 0);
+ new_drvdata->coherent = of_dma_is_coherent(np);
/*Initialize inflight counter used in dx_ablkcipher_secure_complete used for count of BYSPASS blocks operations*/
new_drvdata->inflight_counter = 0;
diff --git a/drivers/staging/ccree/ssi_driver.h b/drivers/staging/ccree/ssi_driver.h
index faf47b1..1b8471b 100644
--- a/drivers/staging/ccree/ssi_driver.h
+++ b/drivers/staging/ccree/ssi_driver.h
@@ -55,6 +55,8 @@
#define DRV_MODULE_VERSION "3.0"
#define SSI_DEV_NAME_STR "cc715ree"
+#define CC_COHERENT_CACHE_PARAMS 0xEEE
+
#define SSI_CC_HAS_AES_CCM 1
#define SSI_CC_HAS_AES_GCM 1
#define SSI_CC_HAS_AES_XTS 1
@@ -150,6 +152,7 @@ struct ssi_drvdata {
void *sram_mgr_handle;
u32 inflight_counter;
struct clk *clk;
+ bool coherent;
};
struct ssi_crypto_alg {
--
2.1.4
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v3 6/6] staging: ccree: use signal safe completion wait
2017-06-25 7:47 [PATCH v3 0/6] staging: ccree: bug fixes and TODO items for 4.13 Gilad Ben-Yossef
` (4 preceding siblings ...)
2017-06-25 7:47 ` [PATCH v3 5/6] staging: ccree: add DT bus coherency detection Gilad Ben-Yossef
@ 2017-06-25 7:47 ` Gilad Ben-Yossef
5 siblings, 0 replies; 7+ messages in thread
From: Gilad Ben-Yossef @ 2017-06-25 7:47 UTC (permalink / raw)
To: Greg Kroah-Hartman, linux-kernel, linux-crypto, driverdev-devel,
devel
Cc: Ofir Drang, Dan Carpenter
We were waiting for a completion notification of HW DMA
operation using an interruptible wait which can result
in data corruption if a signal interrupted us while
DMA was not yet completed.
Fix this by moving to uninterrupted wait.
Fixes: abefd6741d ("staging: ccree: introduce CryptoCell HW driver").
Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
---
drivers/staging/ccree/ssi_request_mgr.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/staging/ccree/ssi_request_mgr.c b/drivers/staging/ccree/ssi_request_mgr.c
index 7c2d88a..2c6937a 100644
--- a/drivers/staging/ccree/ssi_request_mgr.c
+++ b/drivers/staging/ccree/ssi_request_mgr.c
@@ -382,7 +382,8 @@ int send_request(
/* Wait upon sequence completion.
* Return "0" -Operation done successfully.
*/
- return wait_for_completion_interruptible(&ssi_req->seq_compl);
+ wait_for_completion(&ssi_req->seq_compl);
+ return 0;
} else {
/* Operation still in process */
return -EINPROGRESS;
--
2.1.4
^ permalink raw reply related [flat|nested] 7+ messages in thread