* [PATCH v3 1/3] dt-bindings: crypto: ice: document sm8150 compatible
2026-11-11 4:17 [PATCH v3 0/3] arm64: dts: qcom: sm8150: Add standalone ICE node for UFS Andrew Gigena via B4 Relay
@ 2026-11-11 4:17 ` Andrew Gigena via B4 Relay
2026-11-11 11:50 ` Krzysztof Kozlowski
2026-11-11 4:17 ` [PATCH v3 2/3] dt-bindings: ufs: qcom: classify sm8150-ufshc as standalone ICE Andrew Gigena via B4 Relay
2026-11-11 4:17 ` [PATCH v3 3/3] arm64: dts: qcom: sm8150: use standalone ICE for UFS Andrew Gigena via B4 Relay
2 siblings, 1 reply; 7+ messages in thread
From: Andrew Gigena via B4 Relay @ 2026-11-11 4:17 UTC (permalink / raw)
To: Abel Vesa, Herbert Xu, David S. Miller, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam,
Alim Akhtar, Bart Van Assche, Bean Huo, Stanley Jhu,
Bjorn Andersson, Andy Gross, Konrad Dybcio
Cc: linux-arm-msm, linux-crypto, devicetree, linux-kernel, linux-scsi,
Andrew Gigena
From: Andrew Gigena <mail@andrewgigena.dev>
SM8150 uses a standalone ICE node, so its compatible must be listed.
Signed-off-by: Andrew Gigena <mail@andrewgigena.dev>
---
Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
index 23bf98c2b9fa..0d73e4581e6e 100644
--- a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
+++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
@@ -24,6 +24,7 @@ properties:
- qcom,sc7180-inline-crypto-engine
- qcom,sc7280-inline-crypto-engine
- qcom,shikra-inline-crypto-engine
+ - qcom,sm8150-inline-crypto-engine
- qcom,sm8450-inline-crypto-engine
- qcom,sm8550-inline-crypto-engine
- qcom,sm8650-inline-crypto-engine
--
2.56.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH v3 1/3] dt-bindings: crypto: ice: document sm8150 compatible
2026-11-11 4:17 ` [PATCH v3 1/3] dt-bindings: crypto: ice: document sm8150 compatible Andrew Gigena via B4 Relay
@ 2026-11-11 11:50 ` Krzysztof Kozlowski
0 siblings, 0 replies; 7+ messages in thread
From: Krzysztof Kozlowski @ 2026-11-11 11:50 UTC (permalink / raw)
To: Andrew Gigena
Cc: Abel Vesa, Herbert Xu, David S. Miller, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam,
Alim Akhtar, Bart Van Assche, Bean Huo, Stanley Jhu,
Bjorn Andersson, Andy Gross, Konrad Dybcio, linux-arm-msm,
linux-crypto, devicetree, linux-kernel, linux-scsi
On Wed, Nov 11, 2026 at 04:17:49AM +0000, Andrew Gigena wrote:
> SM8150 uses a standalone ICE node, so its compatible must be listed.
>
> Signed-off-by: Andrew Gigena <mail@andrewgigena.dev>
> ---
> Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v3 2/3] dt-bindings: ufs: qcom: classify sm8150-ufshc as standalone ICE
2026-11-11 4:17 [PATCH v3 0/3] arm64: dts: qcom: sm8150: Add standalone ICE node for UFS Andrew Gigena via B4 Relay
2026-11-11 4:17 ` [PATCH v3 1/3] dt-bindings: crypto: ice: document sm8150 compatible Andrew Gigena via B4 Relay
@ 2026-11-11 4:17 ` Andrew Gigena via B4 Relay
2026-11-11 4:35 ` sashiko-bot
2026-11-11 11:55 ` Krzysztof Kozlowski
2026-11-11 4:17 ` [PATCH v3 3/3] arm64: dts: qcom: sm8150: use standalone ICE for UFS Andrew Gigena via B4 Relay
2 siblings, 2 replies; 7+ messages in thread
From: Andrew Gigena via B4 Relay @ 2026-11-11 4:17 UTC (permalink / raw)
To: Abel Vesa, Herbert Xu, David S. Miller, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam,
Alim Akhtar, Bart Van Assche, Bean Huo, Stanley Jhu,
Bjorn Andersson, Andy Gross, Konrad Dybcio
Cc: linux-arm-msm, linux-crypto, devicetree, linux-kernel, linux-scsi,
Andrew Gigena
From: Andrew Gigena <mail@andrewgigena.dev>
SM8150 UFS uses a standalone ICE node, so its compatible belongs to the
standalone-ICE binding rather than the embedded-ICE one.
Signed-off-by: Andrew Gigena <mail@andrewgigena.dev>
---
Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml | 2 ++
Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 11 ++++-------
2 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml b/Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml
index 3c407426d697..572eec814a60 100644
--- a/Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml
+++ b/Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml
@@ -23,6 +23,7 @@ select:
- qcom,sc7280-ufshc
- qcom,sc8180x-ufshc
- qcom,sc8280xp-ufshc
+ - qcom,sm8150-ufshc
- qcom,sm8250-ufshc
- qcom,sm8350-ufshc
- qcom,sm8450-ufshc
@@ -48,6 +49,7 @@ properties:
- qcom,sc7280-ufshc
- qcom,sc8180x-ufshc
- qcom,sc8280xp-ufshc
+ - qcom,sm8150-ufshc
- qcom,sm8250-ufshc
- qcom,sm8350-ufshc
- qcom,sm8450-ufshc
diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
index 516bb61a4624..ef4d1d055169 100644
--- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
+++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
@@ -23,7 +23,6 @@ select:
- qcom,sm6115-ufshc
- qcom,sm6125-ufshc
- qcom,sm6350-ufshc
- - qcom,sm8150-ufshc
required:
- compatible
@@ -38,7 +37,6 @@ properties:
- qcom,sm6115-ufshc
- qcom,sm6125-ufshc
- qcom,sm6350-ufshc
- - qcom,sm8150-ufshc
- const: qcom,ufshc
- const: jedec,ufs-2.0
@@ -69,7 +67,6 @@ allOf:
enum:
- qcom,sdm845-ufshc
- qcom,sm6350-ufshc
- - qcom,sm8150-ufshc
then:
properties:
clocks:
@@ -175,10 +172,10 @@ unevaluatedProperties: false
examples:
- |
- #include <dt-bindings/clock/qcom,gcc-sm8150.h>
+ #include <dt-bindings/clock/qcom,gcc-sdm845.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/gpio/gpio.h>
- #include <dt-bindings/interconnect/qcom,sm8150.h>
+ #include <dt-bindings/interconnect/qcom,sdm845.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
soc {
@@ -186,7 +183,7 @@ examples:
#size-cells = <2>;
ufs@1d84000 {
- compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
+ compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
reg = <0x0 0x01d84000 0x0 0x2500>,
<0x0 0x01d90000 0x0 0x8000>;
@@ -207,7 +204,7 @@ examples:
vccq-max-microamp = <1200000>;
power-domains = <&gcc UFS_PHY_GDSC>;
- iommus = <&apps_smmu 0x300 0>;
+ iommus = <&apps_smmu 0x100 0xf>;
clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
--
2.56.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH v3 2/3] dt-bindings: ufs: qcom: classify sm8150-ufshc as standalone ICE
2026-11-11 4:17 ` [PATCH v3 2/3] dt-bindings: ufs: qcom: classify sm8150-ufshc as standalone ICE Andrew Gigena via B4 Relay
@ 2026-11-11 4:35 ` sashiko-bot
2026-11-11 11:55 ` Krzysztof Kozlowski
1 sibling, 0 replies; 7+ messages in thread
From: sashiko-bot @ 2026-11-11 4:35 UTC (permalink / raw)
To: Andrew Gigena, Abel Vesa, Herbert Xu, David S. Miller,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Manivannan Sadhasivam, Alim Akhtar, Bart Van Assche, Bean Huo,
Stanley Jhu, Bjorn Andersson, Andy Gross, Konrad Dybcio
Cc: linux-crypto, devicetree, linux-scsi
Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Medium] dt-bindings: ufs: qcom: moving sm8150-ufshc breaks existing
2-reg/9-clock DTs
--
commit 830241ce50cfd60c40fb1ab69965eff9ecfda73c
Author: Andrew Gigena <mail@andrewgigena.dev>
dt-bindings: ufs: qcom: classify sm8150-ufshc as standalone ICE
This commit moves the qcom,sm8150-ufshc compatible from
Documentation/devicetree/bindings/ufs/qcom,ufs.yaml to
Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml and updates
the example in qcom,ufs.yaml to use qcom,sdm845-ufshc.
> diff --git a/Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml b/Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml
> index 3c407426d6972..572eec814a604 100644
> --- a/Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml
> +++ b/Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml
> @@ -23,6 +23,7 @@ select:
> - qcom,sc7280-ufshc
> - qcom,sc8180x-ufshc
> - qcom,sc8280xp-ufshc
> + - qcom,sm8150-ufshc
> - qcom,sm8250-ufshc
> - qcom,sm8350-ufshc
> - qcom,sm8450-ufshc
> @@ -48,6 +49,7 @@ properties:
> - qcom,sc7280-ufshc
> - qcom,sc8180x-ufshc
> - qcom,sc8280xp-ufshc
> + - qcom,sm8150-ufshc
> - qcom,sm8250-ufshc
> - qcom,sm8350-ufshc
> - qcom,sm8450-ufshc
[Severity: Medium]
As reported by Krzysztof Kozlowski on v2 [1], does moving
qcom,sm8150-ufshc to qcom,sc7180-ufshc.yaml break dtbs_check for existing
SM8150 and SA8155P device trees?
qcom,sc7180-ufshc.yaml restricts reg to maxItems: 1 and clocks to
maxItems: 8, rejecting the second ice register region and the ninth
ice_core_clk clock used by the embedded-ICE representation (supported
since 462c5c0aa798 ("dt-bindings: ufs: qcom,ufs: convert to dtschema")).
Later commit "arm64: dts: qcom: sm8150: use standalone ICE for UFS" in
this series converts the in-tree sm8150.dtsi to use a standalone ICE node,
but dtbs_check fails at this commit (and across subsystem trees if UFS
bindings and QCOM DTS changes are merged separately) and schema backwards
compatibility with existing 2-reg/9-clock DTBs is broken.
[1] https://lore.kernel.org/r/20261106-offbeat-hawk-of-purring-50a8aa@quoll
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261111-sm8150-ice-rfc-v3-0-f9d5a806fc95@andrewgigena.dev?part=2
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH v3 2/3] dt-bindings: ufs: qcom: classify sm8150-ufshc as standalone ICE
2026-11-11 4:17 ` [PATCH v3 2/3] dt-bindings: ufs: qcom: classify sm8150-ufshc as standalone ICE Andrew Gigena via B4 Relay
2026-11-11 4:35 ` sashiko-bot
@ 2026-11-11 11:55 ` Krzysztof Kozlowski
1 sibling, 0 replies; 7+ messages in thread
From: Krzysztof Kozlowski @ 2026-11-11 11:55 UTC (permalink / raw)
To: Andrew Gigena
Cc: Abel Vesa, Herbert Xu, David S. Miller, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam,
Alim Akhtar, Bart Van Assche, Bean Huo, Stanley Jhu,
Bjorn Andersson, Andy Gross, Konrad Dybcio, linux-arm-msm,
linux-crypto, devicetree, linux-kernel, linux-scsi
On Wed, Nov 11, 2026 at 04:17:50AM +0000, Andrew Gigena wrote:
> SM8150 UFS uses a standalone ICE node, so its compatible belongs to the
> standalone-ICE binding rather than the embedded-ICE one.
>
> Signed-off-by: Andrew Gigena <mail@andrewgigena.dev>
> ---
> Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml | 2 ++
> Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 11 ++++-------
> 2 files changed, 6 insertions(+), 7 deletions(-)
>
This introduces new dtbs_check warning, which is fine but should be
explained that it has no practical impact.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v3 3/3] arm64: dts: qcom: sm8150: use standalone ICE for UFS
2026-11-11 4:17 [PATCH v3 0/3] arm64: dts: qcom: sm8150: Add standalone ICE node for UFS Andrew Gigena via B4 Relay
2026-11-11 4:17 ` [PATCH v3 1/3] dt-bindings: crypto: ice: document sm8150 compatible Andrew Gigena via B4 Relay
2026-11-11 4:17 ` [PATCH v3 2/3] dt-bindings: ufs: qcom: classify sm8150-ufshc as standalone ICE Andrew Gigena via B4 Relay
@ 2026-11-11 4:17 ` Andrew Gigena via B4 Relay
2 siblings, 0 replies; 7+ messages in thread
From: Andrew Gigena via B4 Relay @ 2026-11-11 4:17 UTC (permalink / raw)
To: Abel Vesa, Herbert Xu, David S. Miller, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam,
Alim Akhtar, Bart Van Assche, Bean Huo, Stanley Jhu,
Bjorn Andersson, Andy Gross, Konrad Dybcio
Cc: linux-arm-msm, linux-crypto, devicetree, linux-kernel, linux-scsi,
Andrew Gigena
From: Andrew Gigena <mail@andrewgigena.dev>
Align SM8150 with the standalone ICE representation used on newer
platforms instead of embedding ICE registers in the UFS node.
Signed-off-by: Andrew Gigena <mail@andrewgigena.dev>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 25 ++++++++++++++++---------
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 293fcbacff34..b3d6f3d92395 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -2071,9 +2071,7 @@ pcie1_phy: phy@1c0e000 {
ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
- reg = <0 0x01d84000 0 0x2500>,
- <0 0x01d90000 0 0x8000>;
- reg-names = "std", "ice";
+ reg = <0 0x01d84000 0 0x2500>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufs_mem_phy>;
phy-names = "ufsphy";
@@ -2092,8 +2090,7 @@ ufs_mem_hc: ufshc@1d84000 {
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
- "rx_lane1_sync_clk",
- "ice_core_clk";
+ "rx_lane1_sync_clk";
clocks =
<&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
@@ -2102,8 +2099,7 @@ ufs_mem_hc: ufshc@1d84000 {
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
- <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
- <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
freq-table-hz =
<37500000 300000000>,
<0 0>,
@@ -2112,8 +2108,8 @@ ufs_mem_hc: ufshc@1d84000 {
<0 0>,
<0 0>,
<0 0>,
- <0 0>,
- <0 300000000>;
+ <0 0>;
+ qcom,ice = <&ice>;
status = "disabled";
};
@@ -2139,6 +2135,17 @@ ufs_mem_phy: phy@1d87000 {
status = "disabled";
};
+ ice: crypto@1d90000 {
+ compatible = "qcom,sm8150-inline-crypto-engine",
+ "qcom,inline-crypto-engine";
+ reg = <0 0x01d90000 0 0x8000>;
+ clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
+ <&gcc GCC_UFS_PHY_AHB_CLK>;
+ clock-names = "core",
+ "iface";
+ power-domains = <&gcc UFS_PHY_GDSC>;
+ };
+
cryptobam: dma-controller@1dc4000 {
compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
reg = <0 0x01dc4000 0 0x24000>;
--
2.56.0
^ permalink raw reply related [flat|nested] 7+ messages in thread