From: Dave Jiang <dave.jiang@intel.com>
To: Dan Williams <dan.j.williams@intel.com>, linux-cxl@vger.kernel.org
Cc: stable@vger.kernel.org, vishal.l.verma@intel.com,
alison.schofield@intel.com, ira.weiny@intel.com
Subject: Re: [PATCH 1/7] cxl/region: Fix region HPA ordering validation
Date: Fri, 4 Nov 2022 14:36:28 -0700 [thread overview]
Message-ID: <00353b48-7709-fbca-c261-ffb34a160ffa@intel.com> (raw)
In-Reply-To: <166752182461.947915.497032805239915067.stgit@dwillia2-xfh.jf.intel.com>
On 11/3/2022 5:30 PM, Dan Williams wrote:
> Some regions may not have any address space allocated. Skip them when
> validating HPA order otherwise a crash like the following may result:
>
> devm_cxl_add_region: cxl_acpi cxl_acpi.0: decoder3.4: created region9
> BUG: kernel NULL pointer dereference, address: 0000000000000000
> [..]
> RIP: 0010:store_targetN+0x655/0x1740 [cxl_core]
> [..]
> Call Trace:
> <TASK>
> kernfs_fop_write_iter+0x144/0x200
> vfs_write+0x24a/0x4d0
> ksys_write+0x69/0xf0
> do_syscall_64+0x3a/0x90
>
> store_targetN+0x655/0x1740:
> alloc_region_ref at drivers/cxl/core/region.c:676
> (inlined by) cxl_port_attach_region at drivers/cxl/core/region.c:850
> (inlined by) cxl_region_attach at drivers/cxl/core/region.c:1290
> (inlined by) attach_target at drivers/cxl/core/region.c:1410
> (inlined by) store_targetN at drivers/cxl/core/region.c:1453
>
> Cc: <stable@vger.kernel.org>
> Fixes: 384e624bb211 ("cxl/region: Attach endpoint decoders")
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> ---
> drivers/cxl/core/region.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> index bb6f4fc84a3f..d26ca7a6beae 100644
> --- a/drivers/cxl/core/region.c
> +++ b/drivers/cxl/core/region.c
> @@ -658,6 +658,9 @@ static struct cxl_region_ref *alloc_region_ref(struct cxl_port *port,
> xa_for_each(&port->regions, index, iter) {
> struct cxl_region_params *ip = &iter->region->params;
>
> + if (!ip->res)
> + continue;
> +
> if (ip->res->start > p->res->start) {
> dev_dbg(&cxlr->dev,
> "%s: HPA order violation %s:%pr vs %pr\n",
>
next prev parent reply other threads:[~2022-11-04 21:36 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-04 0:30 [PATCH 0/7] CXL region creation fixes for 6.1 Dan Williams
2022-11-04 0:30 ` [PATCH 1/7] cxl/region: Fix region HPA ordering validation Dan Williams
2022-11-04 5:34 ` Verma, Vishal L
2022-11-04 21:36 ` Dave Jiang [this message]
2022-11-04 0:30 ` [PATCH 2/7] cxl/region: Fix cxl_region leak, cleanup targets at region delete Dan Williams
2022-11-04 5:39 ` Verma, Vishal L
2022-11-04 21:38 ` Dave Jiang
2022-11-04 0:30 ` [PATCH 3/7] cxl/pmem: Fix cxl_pmem_region and cxl_memdev leak Dan Williams
2022-11-04 5:55 ` Verma, Vishal L
2022-11-04 21:42 ` Dave Jiang
2022-11-04 0:30 ` [PATCH 4/7] tools/testing/cxl: Fix some error exits Dan Williams
2022-11-04 5:57 ` Verma, Vishal L
2022-11-04 21:43 ` Dave Jiang
2022-11-04 0:30 ` [PATCH 5/7] tools/testing/cxl: Add a single-port host-bridge regression config Dan Williams
2022-11-04 6:25 ` Verma, Vishal L
2022-11-04 17:52 ` Dan Williams
2022-11-04 0:30 ` [PATCH 6/7] cxl/region: Fix 'distance' calculation with passthrough ports Dan Williams
2022-11-04 6:42 ` Verma, Vishal L
2022-11-04 18:59 ` Dan Williams
2022-11-04 19:31 ` Verma, Vishal L
2022-11-04 21:58 ` Dave Jiang
2022-11-04 22:51 ` Dan Williams
2022-11-04 0:31 ` [PATCH 7/7] cxl/region: Recycle region ids Dan Williams
2022-11-04 6:31 ` Verma, Vishal L
2022-11-04 22:15 ` Dave Jiang
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