[PATCH 1/2] cxl/acpi: Fix XOR 3-6-12 way host bridge look-up calculation

[alison.schofield@intel.com]

From: Alison Schofield <alison.schofield@intel.com>

The XOR host bridge look-up function is broken in its application
of the modulo calculation for interleaves that are multiples of 3.

The failure appears like this:
[] cxl_core:cxl_region_attach_position:1433: cxl region4: mem0:decoder8.1 invalid target position for decoder3.2

Replace the broken modulo calc with the same modulo calc as used
for Modulo Math. This is per CXL spec definition but was overlooked
in the original over-complicated implementation.

With the simple modulo calculation, the jump to a helper function
becomes needless and the work is now presented in a straight line.

Display the interleave_arithmetic in the dev_dbg() of successfully
setup root decoders to make debug lookup easier.

Fixes: f9db85bfec0d ("cxl/acpi: Support CXL XOR Interleave Math (CXIMS)")
Signed-off-by: Alison Schofield <alison.schofield@intel.com>
---
 drivers/cxl/acpi.c | 51 ++++++++++++++++++++--------------------------
 1 file changed, 22 insertions(+), 29 deletions(-)

diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c
index dcf2b39e1048..86c735f733ea 100644
--- a/drivers/cxl/acpi.c
+++ b/drivers/cxl/acpi.c
@@ -22,31 +22,6 @@ static const guid_t acpi_cxl_qtg_id_guid =
 	GUID_INIT(0xF365F9A6, 0xA7DE, 0x4071,
 		  0xA6, 0x6A, 0xB4, 0x0C, 0x0B, 0x4F, 0x8E, 0x52);
 
-/*
- * Find a targets entry (n) in the host bridge interleave list.
- * CXL Specification 3.0 Table 9-22
- */
-static int cxl_xor_calc_n(u64 hpa, struct cxl_cxims_data *cximsd, int iw,
-			  int ig)
-{
-	int i = 0, n = 0;
-	u8 eiw;
-
-	/* IW: 2,4,6,8,12,16 begin building 'n' using xormaps */
-	if (iw != 3) {
-		for (i = 0; i < cximsd->nr_maps; i++)
-			n |= (hweight64(hpa & cximsd->xormaps[i]) & 1) << i;
-	}
-	/* IW: 3,6,12 add a modulo calculation to 'n' */
-	if (!is_power_of_2(iw)) {
-		if (ways_to_eiw(iw, &eiw))
-			return -1;
-		hpa &= GENMASK_ULL(51, eiw + ig);
-		n |= do_div(hpa, 3) << i;
-	}
-	return n;
-}
-
 static struct cxl_dport *cxl_hb_xor(struct cxl_root_decoder *cxlrd, int pos)
 {
 	struct cxl_cxims_data *cximsd = cxlrd->platform_data;
@@ -62,11 +37,28 @@ static struct cxl_dport *cxl_hb_xor(struct cxl_root_decoder *cxlrd, int pos)
 			  "misconfigured root decoder\n"))
 		return NULL;
 
+	/*
+	 * Find a targets entry in the host bridge interleave
+	 * list as defined in CXL Specification 3.0 Table 9-22
+	 *
+	 * iw: 1 is no interleave, so entry is 0
+	 * iw: 3 uses a modulo calc only
+	 * iw: 2,4,6,8,12,16 use xormaps
+	 * iw: 6,12 apply a modulo calc after xormaps
+	 */
+
+	if (iw == 1)
+		return cxlrd->cxlsd.target[0];
+
+	if (iw == 3)
+		return cxlrd->cxlsd.target[pos % iw];
+
 	hpa = cxlrd->res->start + pos * ig;
+	for (int i = 0; i < cximsd->nr_maps; i++)
+		n |= (hweight64(hpa & cximsd->xormaps[i]) & 1) << i;
 
-	/* Entry (n) is 0 for no interleave (iw == 1) */
-	if (iw != 1)
-		n = cxl_xor_calc_n(hpa, cximsd, iw, ig);
+	if (iw == 6 || iw == 12)
+		n |= pos % iw;
 
 	if (n < 0)
 		return NULL;
@@ -424,8 +416,9 @@ static int cxl_parse_cfmws(union acpi_subtable_headers *header, void *arg,
 		dev_err(dev, "Failed to add decode range: %pr", res);
 		return rc;
 	}
-	dev_dbg(dev, "add: %s node: %d range [%#llx - %#llx]\n",
+	dev_dbg(dev, "add: %s math: %s node: %d range [%#llx - %#llx]\n",
 		dev_name(&cxld->dev),
+		cfmws->interleave_arithmetic ? "xor" : "modulo",
 		phys_to_target_node(cxld->hpa_range.start),
 		cxld->hpa_range.start, cxld->hpa_range.end);
 
-- 
2.37.3