RE: [PATCH 1/2] cxl/acpi: Fix XOR 3-6-12 way host bridge look-up calculation

[Dan Williams <dan.j.williams@intel.com>]

Dan Williams wrote:
> alison.schofield@ wrote:
> > From: Alison Schofield <alison.schofield@intel.com>
> > 
> > The XOR host bridge look-up function is broken in its application
> > of the modulo calculation for interleaves that are multiples of 3.
> > 
> > The failure appears like this:
> > [] cxl_core:cxl_region_attach_position:1433: cxl region4: mem0:decoder8.1 invalid target position for decoder3.2
> > 
> > Replace the broken modulo calc with the same modulo calc as used
> > for Modulo Math. This is per CXL spec definition but was overlooked
> > in the original over-complicated implementation.
> > 
> > With the simple modulo calculation, the jump to a helper function
> > becomes needless and the work is now presented in a straight line.
> > 
> > Display the interleave_arithmetic in the dev_dbg() of successfully
> > setup root decoders to make debug lookup easier.
> > 
> > Fixes: f9db85bfec0d ("cxl/acpi: Support CXL XOR Interleave Math (CXIMS)")
> > Signed-off-by: Alison Schofield <alison.schofield@intel.com>
[..]
> > -	/* Entry (n) is 0 for no interleave (iw == 1) */
> > -	if (iw != 1)
> > -		n = cxl_xor_calc_n(hpa, cximsd, iw, ig);
> > +	if (iw == 6 || iw == 12)
> > +		n |= pos % iw;
> 
> Can you help me map this back to Table-9-22?
> 
> Shouldn't this be:
> 
> 	n |= (pos % iw) << (iw / 3);

Wait, no:

 	n |= (pos % iw) * (iw / 3);

...to match:

 6:   + 2* HPA[51:9+HBIG] MOD 3

 12:  + 4* HPA[51:10+HBIG] MOD 3