From: Ben Widawsky <ben.widawsky@intel.com>
To: linux-cxl@vger.kernel.org, Dan Williams <dan.j.williams@intel.com>
Cc: Ben Widawsky <ben.widawsky@intel.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Ira Weiny <ira.weiny@intel.com>
Subject: [PATCH] cxl/component_regs: Fix offset
Date: Thu, 10 Jun 2021 22:11:13 -0700 [thread overview]
Message-ID: <20210611051113.224328-1-ben.widawsky@intel.com> (raw)
The CXL.cache and CXL.mem registers begin after the CXL.io registers
which occupy the first 0x1000 bytes. The current code wasn't setting
this up properly for future users of the component registers. It was
correct for the probing code however.
Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Ira Weiny <ira.weiny@intel.com>
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
---
drivers/cxl/core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/cxl/core.c b/drivers/cxl/core.c
index 92db02fe7aa8..c7f956fa3ada 100644
--- a/drivers/cxl/core.c
+++ b/drivers/cxl/core.c
@@ -671,7 +671,7 @@ void cxl_probe_component_regs(struct device *dev, void __iomem *base,
length = 0x20 * decoder_cnt + 0x10;
map->hdm_decoder.valid = true;
- map->hdm_decoder.offset = offset;
+ map->hdm_decoder.offset = CXL_CM_OFFSET + offset;
map->hdm_decoder.size = length;
break;
default:
--
2.32.0
next reply other threads:[~2021-06-11 5:11 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-11 5:11 Ben Widawsky [this message]
2021-06-11 13:03 ` [PATCH] cxl/component_regs: Fix offset Jonathan Cameron
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