* [PATCH] cxl/component_regs: Fix offset
@ 2021-06-11 5:11 Ben Widawsky
2021-06-11 13:03 ` Jonathan Cameron
0 siblings, 1 reply; 2+ messages in thread
From: Ben Widawsky @ 2021-06-11 5:11 UTC (permalink / raw)
To: linux-cxl, Dan Williams; +Cc: Ben Widawsky, Jonathan Cameron, Ira Weiny
The CXL.cache and CXL.mem registers begin after the CXL.io registers
which occupy the first 0x1000 bytes. The current code wasn't setting
this up properly for future users of the component registers. It was
correct for the probing code however.
Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Ira Weiny <ira.weiny@intel.com>
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
---
drivers/cxl/core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/cxl/core.c b/drivers/cxl/core.c
index 92db02fe7aa8..c7f956fa3ada 100644
--- a/drivers/cxl/core.c
+++ b/drivers/cxl/core.c
@@ -671,7 +671,7 @@ void cxl_probe_component_regs(struct device *dev, void __iomem *base,
length = 0x20 * decoder_cnt + 0x10;
map->hdm_decoder.valid = true;
- map->hdm_decoder.offset = offset;
+ map->hdm_decoder.offset = CXL_CM_OFFSET + offset;
map->hdm_decoder.size = length;
break;
default:
--
2.32.0
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] cxl/component_regs: Fix offset
2021-06-11 5:11 [PATCH] cxl/component_regs: Fix offset Ben Widawsky
@ 2021-06-11 13:03 ` Jonathan Cameron
0 siblings, 0 replies; 2+ messages in thread
From: Jonathan Cameron @ 2021-06-11 13:03 UTC (permalink / raw)
To: Ben Widawsky; +Cc: linux-cxl, Dan Williams, Ira Weiny
On Thu, 10 Jun 2021 22:11:13 -0700
Ben Widawsky <ben.widawsky@intel.com> wrote:
> The CXL.cache and CXL.mem registers begin after the CXL.io registers
> which occupy the first 0x1000 bytes. The current code wasn't setting
> this up properly for future users of the component registers. It was
> correct for the probing code however.
>
> Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Cc: Ira Weiny <ira.weiny@intel.com>
> Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
I guess we could have assumed that this offset was always form CXL_CM_OFFSET
but as that's a bit odd, this change makes sense.
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
> drivers/cxl/core.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/cxl/core.c b/drivers/cxl/core.c
> index 92db02fe7aa8..c7f956fa3ada 100644
> --- a/drivers/cxl/core.c
> +++ b/drivers/cxl/core.c
> @@ -671,7 +671,7 @@ void cxl_probe_component_regs(struct device *dev, void __iomem *base,
> length = 0x20 * decoder_cnt + 0x10;
>
> map->hdm_decoder.valid = true;
> - map->hdm_decoder.offset = offset;
> + map->hdm_decoder.offset = CXL_CM_OFFSET + offset;
> map->hdm_decoder.size = length;
> break;
> default:
^ permalink raw reply [flat|nested] 2+ messages in thread
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2021-06-11 13:03 ` Jonathan Cameron
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