From: Ben Widawsky <ben.widawsky@intel.com>
To: linux-cxl@vger.kernel.org
Cc: Ben Widawsky <ben.widawsky@intel.com>,
Alison Schofield <alison.schofield@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Jonathan Cameron <Jonathan.Cameron@Huawei.com>,
Vishal Verma <vishal.l.verma@intel.com>
Subject: [PATCH 0/6] Region creation
Date: Thu, 17 Jun 2021 10:36:49 -0700 [thread overview]
Message-ID: <20210617173655.430424-1-ben.widawsky@intel.com> (raw)
CXL interleave sets and non-interleave sets are described via regions. A region
is specified in the CXL 2.0 specification and the purpose is to create a
standardized way to preserve the region across reboots.
Introduced here is the basic mechanism to create configure and delete a CXL
region. Configuring a region simply means giving it a size, UUID, and a target
list. Enabling/activating a region is comprised of three parts:
1. Validate and find space for the region in the CFMWS (included here)
2. Program the HDM decoders (WIP)
3. Adding the region label to the LSA (Dan WIP)
Here is a sample topology
decoder1.0
├── create_region
├── delete_region
├── devtype
├── locked
├── region1.0:0
│ ├── offset
│ ├── size
│ ├── subsystem -> ../../../../../../../bus/cxl
│ ├── target0
│ ├── uevent
│ ├── uuid
│ └── verify
├── size
├── start
├── subsystem -> ../../../../../../bus/cxl
├── target_list
├── target_type
└── uevent
Next Steps.
Next task is to create a CXL memory driver which will enumerate CXL capable
endpoints. A CXL capable endpoint is similar to the existing cxl_mem structure
except that it's known that there exists a path from a hostbridge down to the
endpoint that is CXL.mem capable. Once that path is established, the HDM decoder
programming can be determined from top of the hierarchy down.
Ben Widawsky (6):
cxl/region: Add region creation ABI
cxl: Move cxl_memdev conversion helper to mem.h
cxl/region: Introduce concept of region configuration
cxl/region: Introduce a cxl_region driver
cxl/core: Convert decoder range to resource
cxl/region: Handle region's address space allocation
Documentation/ABI/testing/sysfs-bus-cxl | 53 ++
.../driver-api/cxl/memory-devices.rst | 11 +
drivers/cxl/Makefile | 5 +-
drivers/cxl/core.c | 108 +++-
drivers/cxl/cxl.h | 18 +-
drivers/cxl/mem.h | 6 +
drivers/cxl/pci.c | 5 -
drivers/cxl/region.c | 492 ++++++++++++++++++
drivers/cxl/region.h | 45 ++
drivers/cxl/trace.h | 33 ++
10 files changed, 760 insertions(+), 16 deletions(-)
create mode 100644 drivers/cxl/region.c
create mode 100644 drivers/cxl/region.h
create mode 100644 drivers/cxl/trace.h
--
2.32.0
next reply other threads:[~2021-06-17 17:38 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-17 17:36 Ben Widawsky [this message]
2021-06-17 17:36 ` [PATCH 1/6] cxl/region: Add region creation ABI Ben Widawsky
2021-06-17 21:11 ` [PATCH v2 " Ben Widawsky
2021-06-18 9:13 ` [PATCH " Jonathan Cameron
2021-06-18 15:07 ` Ben Widawsky
2021-06-18 16:39 ` Dan Williams
2021-06-17 17:36 ` [PATCH 2/6] cxl: Move cxl_memdev conversion helper to mem.h Ben Widawsky
2021-06-18 9:13 ` Jonathan Cameron
2021-06-18 15:00 ` Dan Williams
2021-06-17 17:36 ` [PATCH 3/6] cxl/region: Introduce concept of region configuration Ben Widawsky
2021-06-18 11:22 ` Jonathan Cameron
2021-06-18 15:25 ` Ben Widawsky
2021-06-18 15:44 ` Jonathan Cameron
2021-06-17 17:36 ` [PATCH 4/6] cxl/region: Introduce a cxl_region driver Ben Widawsky
2021-06-17 21:13 ` [PATCH v2 " Ben Widawsky
2021-06-18 11:49 ` Jonathan Cameron
2021-06-17 17:36 ` [PATCH 5/6] cxl/core: Convert decoder range to resource Ben Widawsky
2021-06-18 11:52 ` Jonathan Cameron
2021-06-17 17:36 ` [PATCH 6/6] cxl/region: Handle region's address space allocation Ben Widawsky
2021-06-18 13:35 ` Jonathan Cameron
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