Re: [PATCH 6/6] cxl/registers: Fix Documentation warning

[Jonathan Cameron <Jonathan.Cameron@Huawei.com>]

On Fri, 3 Sep 2021 19:21:06 -0700
Dan Williams <dan.j.williams@intel.com> wrote:

> Commit 0f06157e0135 ("cxl/core: Move register mapping infrastructure")
> neglected to add a DOC header for the new drivers/core/regs.c file.
> 
> Reported-by: Ben Widawsky <ben.widawsky@intel.com>
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Same grumpy comment applies to this one.

Otherwise description is fine.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
>  Documentation/driver-api/cxl/memory-devices.rst |    2 +-
>  drivers/cxl/core/regs.c                         |   15 ++++++++++++++-
>  2 files changed, 15 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/driver-api/cxl/memory-devices.rst b/Documentation/driver-api/cxl/memory-devices.rst
> index df799cdf1c3f..50ebcda17ad0 100644
> --- a/Documentation/driver-api/cxl/memory-devices.rst
> +++ b/Documentation/driver-api/cxl/memory-devices.rst
> @@ -43,7 +43,7 @@ CXL Core
>     :doc: cxl pmem
>  
>  .. kernel-doc:: drivers/cxl/core/regs.c
> -   :internal:
> +   :doc: cxl registers
>  
>  External Interfaces
>  ===================
> diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
> index 8535a7b94f28..41de4a136ecd 100644
> --- a/drivers/cxl/core/regs.c
> +++ b/drivers/cxl/core/regs.c
> @@ -1,12 +1,25 @@
>  // SPDX-License-Identifier: GPL-2.0-only
>  /* Copyright(c) 2020 Intel Corporation. */
> -

hmm

>  #include <linux/io-64-nonatomic-lo-hi.h>
>  #include <linux/device.h>
>  #include <linux/slab.h>
>  #include <linux/pci.h>
>  #include <cxlmem.h>
>  
> +/**
> + * DOC: cxl registers
> + *
> + * CXL device capabilities are enumerated by PCI DVSEC (Designated
> + * Vendor-specific) and / or descriptors provided by platform firmware.
> + * They can be defined as a set like the device and component registers
> + * mandated by CXL Section 8.1.12.2 Memory Device PCIe Capabilities and
> + * Extended Capabilities, or they can be individual capabilities
> + * appended to bridged and endpoint devices.
> + *
> + * Provide common infrastructure for enumerating and mapping these
> + * discrete capabilities.
> + */
> +
>  /**
>   * cxl_probe_component_regs() - Detect CXL Component register blocks
>   * @dev: Host device of the @base mapping
>