From: Bjorn Helgaas <helgaas@kernel.org>
To: Dan Williams <dan.j.williams@intel.com>
Cc: Ben Widawsky <ben.widawsky@intel.com>,
linux-cxl@vger.kernel.org, Ira Weiny <ira.weiny@intel.com>,
Alison Schofield <alison.schofield@intel.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Bjorn Helgaas <bhelgaas@google.com>
Subject: Re: [PATCH] cxl: Move register block enumeration to core
Date: Tue, 21 Sep 2021 17:00:07 -0500 [thread overview]
Message-ID: <20210921220007.GA135188@bhelgaas> (raw)
In-Reply-To: <CAPcyv4ja65PA5qjKPW4dYsVUCEiEDKD65_5vw15VryYL1h7=QQ@mail.gmail.com>
On Tue, Sep 21, 2021 at 07:07:13AM -0700, Dan Williams wrote:
> On Mon, Sep 20, 2021 at 3:57 PM Ben Widawsky <ben.widawsky@intel.com> wrote:
> >
> > CXL drivers or cxl_core itself will require the ability to map component
> > registers in order to map HDM decoder resources amongst other things.
> > Much of the register mapping code has already moved into cxl_core. The
> > code to pull the BAR number and block office remained within cxl_pci
> > because there was no need to move it. Upcoming work will require this
> > functionality to be available outside of cxl_pci.
> >
> > There are two intentional functional changes:
> > 1. cxl_pci: If there is more than 1 component, or device register block,
> > only the first one (of each) is checked. Previous logic checked all
> > duplicate register blocks and additionally attempted to map unused
> > register blocks if present.
> > 2. cxl_pci: No more dev_dbg for unused register blocks
>
> Why not break these out into separate patches before moving the code?
> It makes it easier to review, and it increases the precision of future
> Fixes: patches if necessary.
+1
> > +static int cxl_pci_dvsec(struct pci_dev *pdev, int dvsec)
> > +{
> > + int pos;
> > +
> > + pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DVSEC);
> > + if (!pos)
> > + return 0;
> > +
> > + while (pos) {
> > + u16 vendor, id;
> > +
> > + pci_read_config_word(pdev, pos + PCI_DVSEC_HEADER1, &vendor);
> > + pci_read_config_word(pdev, pos + PCI_DVSEC_HEADER2, &id);
> > + if (vendor == PCI_DVSEC_VENDOR_ID_CXL && dvsec == id)
> > + return pos;
> > +
> > + pos = pci_find_next_ext_capability(pdev, pos,
> > + PCI_EXT_CAP_ID_DVSEC);
> > + }
>
> We punted on refactoring this for the initial driver submission
> because it was difficult to coordinate. Now that cxl.git is an
> established tree, instead of moving this it seems time to address that
> refactor that Bjorn asked about. Bjorn, would you be willing to carry
> a non-rebasing branch with such a cleanup that CXL could pull from?
Sure. Would be nice to get this cleaned up.
prev parent reply other threads:[~2021-09-21 22:00 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-20 22:56 [PATCH] cxl: Move register block enumeration to core Ben Widawsky
2021-09-20 23:15 ` Ben Widawsky
2021-09-21 14:07 ` Dan Williams
2021-09-21 16:44 ` Ben Widawsky
2021-09-21 18:42 ` Dan Williams
2021-09-21 19:06 ` Ben Widawsky
2021-09-21 19:16 ` Dan Williams
2021-09-21 19:21 ` Ben Widawsky
2021-09-21 20:09 ` Dan Williams
2021-09-21 22:00 ` Bjorn Helgaas [this message]
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