From: Ben Widawsky <ben.widawsky@intel.com>
To: Dan Williams <dan.j.williams@intel.com>
Cc: linux-cxl@vger.kernel.org,
Chet Douglas <chet.r.douglas@intel.com>,
Alison Schofield <alison.schofield@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Vishal Verma <vishal.l.verma@intel.com>
Subject: Re: [RFC PATCH v2 01/28] cxl: Rename CXL_MEM to CXL_PCI
Date: Fri, 29 Oct 2021 14:20:42 -0700 [thread overview]
Message-ID: <20211029212042.so56mkjju3ja2k54@intel.com> (raw)
In-Reply-To: <CAPcyv4i_ZnMkTwOcg=94AO959Gzt1FFkirEO=FL3sjNcMsCAeA@mail.gmail.com>
On 21-10-29 13:15:46, Dan Williams wrote:
> On Fri, Oct 22, 2021 at 11:37 AM Ben Widawsky <ben.widawsky@intel.com> wrote:
> >
> > With the upcoming introduction of a driver to control the non-PCI
> > aspects of CXL.mem, such as interleave set creation and configuration,
> > there will be an opportunity to disconnection control over CXL device
>
> s/disconnection/disconnect/
>
> > memory and CXL device manageability. CXL device manageability is
> > implemented by the cxl_pci driver. Doing this rename allows the CXL
> > memory driver to be enabled by a new config option independently of CXL
> > device manageability through CXL.io/PCI mechanisms.
>
> That comes across a bit hard to parse to me, how about:
>
> "The cxl_mem module was renamed cxl_pci in commit 21e9f76733a8 ("cxl:
> Rename mem to pci"). In preparation for adding an ancillary driver for
> cxl_memdev devices (registered on the cxl bus by cxl_pci), go ahead
> and rename CONFIG_CXL_MEM to CONFIG_CXL_PCI. Tree up the CXL_MEM name
I assume you meant s/tree/tee - right?
> for that new driver to manage generic CXL.mem endpoint operations."
>
> > Suggested-by: Dan Williams <dan.j.williams@intel.com>
> > Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
> > ---
> > drivers/cxl/Kconfig | 13 ++++++-------
> > drivers/cxl/Makefile | 2 +-
> > 2 files changed, 7 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig
> > index e6de221cc568..23773d0ac896 100644
> > --- a/drivers/cxl/Kconfig
> > +++ b/drivers/cxl/Kconfig
> > @@ -13,14 +13,13 @@ menuconfig CXL_BUS
> >
> > if CXL_BUS
> >
> > -config CXL_MEM
> > - tristate "CXL.mem: Memory Devices"
> > +config CXL_PCI
> > + tristate "PCI manageability"
>
> s/PCI manageability/CXL Memory Device: PCI Operations/
>
> ...as I don't think an end user reading "PCI Manageability" would know
> that it supports basic memory expander enumeration and mailbox
> operations.
>
> > default CXL_BUS
> > help
> > - The CXL.mem protocol allows a device to act as a provider of
> > - "System RAM" and/or "Persistent Memory" that is fully coherent
> > - as if the memory was attached to the typical CPU memory
> > - controller.
> > + The CXL specification defines a set of interfaces which are controlled
> > + through well known PCI configuration mechanisms. Such access is
> > + referred to CXL.io in the specification.
>
> The CXL specification defines a "CXL memory device" sub-class in the
> PCI "memory controller" base class of devices. Device's identified by
> this class code provide support for volatile and / or persistent
> memory to be mapped into the system address map (Host-managed Device
> Memory (HDM)).
>
> >
> > Say 'y/m' to enable a driver that will attach to CXL.mem devices for
>
> This would need updating too...
>
> s/CXL.mem devices /generic CXL memory expanders identified by the
> memory device class code/
>
> ...to reduce confusion about this driver for generic type-3 vs vendor
> specific type-2 devices that also support CXL.mem
>
Overall seems like an improvement to me. I'm not too fond of the word "generic"
though, both here and in the commit message. I think they work equally well just
deleting that word.
> > configuration and management primarily via the mailbox interface. See
> > @@ -31,7 +30,7 @@ config CXL_MEM
> >
> > config CXL_MEM_RAW_COMMANDS
> > bool "RAW Command Interface for Memory Devices"
> > - depends on CXL_MEM
> > + depends on CXL_PCI
> > help
> > Enable CXL RAW command interface.
> >
> > diff --git a/drivers/cxl/Makefile b/drivers/cxl/Makefile
> > index d1aaabc940f3..cf07ae6cea17 100644
> > --- a/drivers/cxl/Makefile
> > +++ b/drivers/cxl/Makefile
> > @@ -1,6 +1,6 @@
> > # SPDX-License-Identifier: GPL-2.0
> > obj-$(CONFIG_CXL_BUS) += core/
> > -obj-$(CONFIG_CXL_MEM) += cxl_pci.o
> > +obj-$(CONFIG_CXL_PCI) += cxl_pci.o
> > obj-$(CONFIG_CXL_ACPI) += cxl_acpi.o
> > obj-$(CONFIG_CXL_PMEM) += cxl_pmem.o
> >
> > --
> > 2.33.1
> >
next prev parent reply other threads:[~2021-10-29 21:20 UTC|newest]
Thread overview: 112+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-22 18:36 [RFC PATCH v2 00/28] CXL Region Creation / HDM decoder programming Ben Widawsky
2021-10-22 18:36 ` [RFC PATCH v2 01/28] cxl: Rename CXL_MEM to CXL_PCI Ben Widawsky
2021-10-29 20:15 ` Dan Williams
2021-10-29 21:20 ` Ben Widawsky [this message]
2021-10-29 21:39 ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 02/28] cxl: Move register block enumeration to core Ben Widawsky
2021-10-29 20:23 ` Dan Williams
2021-10-29 21:23 ` Ben Widawsky
2021-10-22 18:36 ` [RFC PATCH v2 03/28] cxl/acpi: Map component registers for Root Ports Ben Widawsky
2021-10-29 20:28 ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 04/28] cxl: Add helper for new drivers Ben Widawsky
2021-10-29 20:30 ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 05/28] cxl/core: Convert decoder range to resource Ben Widawsky
2021-10-29 20:50 ` Dan Williams
2021-10-29 21:26 ` Ben Widawsky
2021-10-29 22:22 ` Dan Williams
2021-10-29 22:37 ` Ben Widawsky
2021-11-01 14:33 ` Ben Widawsky
2021-10-22 18:36 ` [RFC PATCH v2 06/28] cxl: Introduce endpoint decoders Ben Widawsky
2021-10-29 21:00 ` Dan Williams
2021-10-29 22:02 ` Ben Widawsky
2021-10-29 22:25 ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 07/28] cxl/core: Move target population locking to caller Ben Widawsky
2021-10-29 23:03 ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 08/28] cxl/port: Introduce a port driver Ben Widawsky
2021-10-30 1:37 ` Dan Williams
2021-10-31 17:53 ` Dan Williams
2021-10-31 18:10 ` Dan Williams
2021-11-01 17:36 ` Ben Widawsky
2021-11-01 17:53 ` Ben Widawsky
2021-11-01 17:54 ` Ben Widawsky
2021-11-02 3:31 ` Dan Williams
2021-11-02 16:27 ` Ben Widawsky
2021-11-02 17:21 ` Dan Williams
2021-11-02 16:58 ` Ben Widawsky
2021-11-04 19:10 ` Dan Williams
2021-11-04 19:49 ` Ben Widawsky
2021-11-04 20:04 ` Dan Williams
2021-11-04 21:25 ` Ben Widawsky
2021-11-04 16:37 ` Ben Widawsky
2021-11-04 19:17 ` Dan Williams
2021-11-04 19:46 ` Ben Widawsky
2021-11-04 20:00 ` Dan Williams
2021-11-04 21:26 ` Ben Widawsky
2021-11-03 15:18 ` Jonathan Cameron
2021-10-22 18:36 ` [RFC PATCH v2 09/28] cxl/acpi: Map single port host bridge component registers Ben Widawsky
2021-10-31 18:03 ` Dan Williams
2021-11-01 17:07 ` Ben Widawsky
2021-11-02 2:15 ` Dan Williams
2021-11-02 16:31 ` Ben Widawsky
2021-11-02 17:46 ` Dan Williams
2021-11-02 17:57 ` Ben Widawsky
2021-11-02 18:10 ` Dan Williams
2021-11-02 18:27 ` Ben Widawsky
2021-11-02 18:49 ` Dan Williams
2021-11-02 21:15 ` Ben Widawsky
2021-11-02 21:34 ` Dan Williams
2021-11-02 21:47 ` Ben Widawsky
2021-10-22 18:36 ` [RFC PATCH v2 10/28] cxl/core: Store global list of root ports Ben Widawsky
2021-10-31 18:32 ` Dan Williams
2021-11-01 18:43 ` Ben Widawsky
2021-11-02 2:04 ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 11/28] cxl/acpi: Rescan bus at probe completion Ben Widawsky
2021-10-31 19:25 ` Dan Williams
2021-11-01 18:56 ` Ben Widawsky
2021-11-01 21:45 ` Ben Widawsky
2021-11-02 1:56 ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 12/28] cxl/core: Store component register base for memdevs Ben Widawsky
2021-10-31 20:13 ` Dan Williams
2021-11-01 21:50 ` Ben Widawsky
2021-10-22 18:36 ` [RFC PATCH v2 13/28] cxl: Flesh out register names Ben Widawsky
2021-10-31 20:18 ` Dan Williams
2021-11-01 22:00 ` Ben Widawsky
2021-11-02 1:53 ` Dan Williams
2021-11-03 15:53 ` Jonathan Cameron
2021-11-03 16:03 ` Ben Widawsky
2021-11-03 16:42 ` Jonathan Cameron
2021-11-03 17:05 ` Ben Widawsky
2021-10-22 18:36 ` [RFC PATCH v2 14/28] cxl: Hide devm host for ports Ben Widawsky
2021-10-31 21:14 ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 15/28] cxl/core: Introduce API to scan switch ports Ben Widawsky
2021-11-01 5:39 ` Dan Williams
2021-11-01 22:56 ` Ben Widawsky
2021-11-02 1:45 ` Dan Williams
2021-11-02 16:39 ` Ben Widawsky
2021-11-02 20:00 ` Dan Williams
2021-11-16 16:50 ` Ben Widawsky
2021-11-16 17:51 ` Dan Williams
2021-11-16 18:02 ` Ben Widawsky
2021-11-03 16:08 ` Jonathan Cameron
2021-11-10 17:49 ` Ben Widawsky
2021-11-10 18:10 ` Jonathan Cameron
2021-11-10 21:03 ` Dan Williams
2021-10-22 18:36 ` [RFC PATCH v2 16/28] cxl: Introduce cxl_mem driver Ben Widawsky
2021-10-22 18:36 ` [RFC PATCH v2 17/28] cxl: Disable switch hierarchies for now Ben Widawsky
2021-10-22 18:36 ` [RFC PATCH v2 18/28] cxl/region: Add region creation ABI Ben Widawsky
2021-10-22 18:37 ` [RFC PATCH v2 19/28] cxl/region: Introduce concept of region configuration Ben Widawsky
2021-12-15 17:47 ` Jonathan Cameron
2021-10-22 18:37 ` [RFC PATCH v2 20/28] cxl/region: Introduce a cxl_region driver Ben Widawsky
2021-10-22 18:37 ` [RFC PATCH v2 21/28] cxl/acpi: Handle address space allocation Ben Widawsky
2021-10-22 18:37 ` [RFC PATCH v2 22/28] cxl/region: Address " Ben Widawsky
2021-10-22 18:37 ` [RFC PATCH v2 23/28] cxl/region: Implement XHB verification Ben Widawsky
2022-01-06 16:55 ` Jonathan Cameron
2022-01-06 16:58 ` Ben Widawsky
2022-01-06 17:33 ` Jonathan Cameron
2022-01-06 18:10 ` Jonathan Cameron
2022-01-06 18:34 ` Ben Widawsky
2021-10-22 18:37 ` [RFC PATCH v2 24/28] cxl/region: HB port config verification Ben Widawsky
2021-10-22 18:37 ` [RFC PATCH v2 25/28] cxl/region: Record host bridge target list Ben Widawsky
2021-10-22 18:37 ` [RFC PATCH v2 26/28] cxl/mem: Store the endpoint's uport Ben Widawsky
2021-10-22 18:37 ` [RFC PATCH v2 27/28] cxl/region: Gather HDM decoder resources Ben Widawsky
2021-10-22 18:37 ` [RFC PATCH v2 28/28] cxl: Program decoders for regions Ben Widawsky
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