Linux CXL
 help / color / mirror / Atom feed
From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: qemu-devel@nongnu.org, "Alex Bennée" <alex.bennee@linaro.org>,
	"Marcel Apfelbaum" <marcel@redhat.com>,
	"Michael S . Tsirkin" <mst@redhat.com>,
	"Igor Mammedov" <imammedo@redhat.com>
Cc: linux-cxl@vger.kernel.org,
	"Ben Widawsky" <ben.widawsky@intel.com>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	linuxarm@huawei.com,
	"Shameerali Kolothum Thodi"
	<shameerali.kolothum.thodi@huawei.com>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"Saransh Gupta1" <saransh@ibm.com>,
	"Shreyas Shah" <shreyas.shah@elastics.cloud>,
	"Chris Browy" <cbrowy@avery-design.com>,
	"Samarth Saxena" <samarths@cadence.com>,
	"Dan Williams" <dan.j.williams@intel.com>
Subject: [PATCH v6 29/43] hw/pci-host/gpex-acpi: Add support for dsdt construction for pxb-cxl
Date: Fri, 11 Feb 2022 12:07:33 +0000	[thread overview]
Message-ID: <20220211120747.3074-30-Jonathan.Cameron@huawei.com> (raw)
In-Reply-To: <20220211120747.3074-1-Jonathan.Cameron@huawei.com>

This adds code to instantiate the slightly extended ACPI root port
description in DSDT as per the CXL 2.0 specification.

Basically a cut and paste job from the i386/pc code.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
---
 hw/arm/Kconfig          |  1 +
 hw/pci-host/gpex-acpi.c | 22 +++++++++++++++++++---
 2 files changed, 20 insertions(+), 3 deletions(-)

diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 2e0049196d..3df419fa6d 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -29,6 +29,7 @@ config ARM_VIRT
     select ACPI_APEI
     select ACPI_VIOT
     select VIRTIO_MEM_SUPPORTED
+    select ACPI_CXL
 
 config CHEETAH
     bool
diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c
index e7e162a00a..fb60aa517f 100644
--- a/hw/pci-host/gpex-acpi.c
+++ b/hw/pci-host/gpex-acpi.c
@@ -5,6 +5,7 @@
 #include "hw/pci/pci_bus.h"
 #include "hw/pci/pci_bridge.h"
 #include "hw/pci/pcie_host.h"
+#include "hw/acpi/cxl.h"
 
 static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t irq)
 {
@@ -139,6 +140,7 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
         QLIST_FOREACH(bus, &bus->child, sibling) {
             uint8_t bus_num = pci_bus_num(bus);
             uint8_t numa_node = pci_bus_numa_node(bus);
+            bool is_cxl;
 
             if (!pci_bus_is_root(bus)) {
                 continue;
@@ -153,9 +155,19 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
                 nr_pcie_buses = bus_num;
             }
 
+            is_cxl = pci_bus_is_cxl(bus);
+
             dev = aml_device("PC%.02X", bus_num);
-            aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
-            aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
+            if (is_cxl) {
+                struct Aml *pkg = aml_package(2);
+                aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0016")));
+                aml_append(pkg, aml_eisaid("PNP0A08"));
+                aml_append(pkg, aml_eisaid("PNP0A03"));
+                aml_append(dev, aml_name_decl("_CID", pkg));
+            } else {
+                aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
+                aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
+            }
             aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
             aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
             aml_append(dev, aml_name_decl("_STR", aml_unicode("pxb Device")));
@@ -175,7 +187,11 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
                             cfg->pio.base, 0, 0, 0);
             aml_append(dev, aml_name_decl("_CRS", crs));
 
-            acpi_dsdt_add_pci_osc(dev);
+            if (is_cxl) {
+                build_cxl_osc_method(dev);
+            } else {
+                acpi_dsdt_add_pci_osc(dev);
+            }
 
             aml_append(scope, dev);
         }
-- 
2.32.0


  parent reply	other threads:[~2022-02-11 12:22 UTC|newest]

Thread overview: 76+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-11 12:07 [PATCH v6 00/43] CXl 2.0 emulation Support Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 01/43] hw/pci/cxl: Add a CXL component type (interface) Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 02/43] hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5) Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 03/43] MAINTAINERS: Add entry for Compute Express Link Emulation Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 04/43] hw/cxl/device: Introduce a CXL device (8.2.8) Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 05/43] hw/cxl/device: Implement the CAP array (8.2.8.1-2) Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 06/43] hw/cxl/device: Implement basic mailbox (8.2.8.4) Jonathan Cameron
2022-03-01 15:32   ` Alex Bennée
2022-03-03 16:31     ` Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 07/43] hw/cxl/device: Add memory device utilities Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 08/43] hw/cxl/device: Add cheap EVENTS implementation (8.2.9.1) Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 09/43] hw/cxl/device: Timestamp implementation (8.2.9.3) Jonathan Cameron
2022-03-01 15:54   ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 10/43] hw/cxl/device: Add log commands (8.2.9.4) + CEL Jonathan Cameron
2022-03-01 17:45   ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 11/43] hw/pxb: Use a type for realizing expanders Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 12/43] hw/pci/cxl: Create a CXL bus type Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 13/43] cxl: Machine level control on whether CXL support is enabled Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 14/43] hw/pxb: Allow creation of a CXL PXB (host bridge) Jonathan Cameron
2022-03-01 17:47   ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 15/43] qtest/cxl: Introduce initial test for pxb-cxl only Jonathan Cameron
2022-03-01 18:00   ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 16/43] hw/cxl/rp: Add a root port Jonathan Cameron
2022-03-01 18:08   ` Alex Bennée
2022-03-03 17:22     ` Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 17/43] hw/cxl/device: Add a memory device (8.2.8.5) Jonathan Cameron
2022-02-11 16:50   ` Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 18/43] qtests/cxl: Add initial root port and CXL type3 tests Jonathan Cameron
2022-03-01 18:11   ` Alex Bennée
2022-03-03 17:53     ` Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 19/43] hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12) Jonathan Cameron
2022-03-01 18:17   ` Alex Bennée
2022-03-03 18:07     ` Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 20/43] hw/cxl/device: Add some trivial commands Jonathan Cameron
2022-03-01 18:46   ` Alex Bennée
2022-03-04 13:16     ` Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 21/43] hw/cxl/device: Plumb real Label Storage Area (LSA) sizing Jonathan Cameron
2022-03-02 10:01   ` Alex Bennée
2022-03-04 13:30     ` Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 22/43] hw/cxl/device: Implement get/set Label Storage Area (LSA) Jonathan Cameron
2022-03-02 10:03   ` Alex Bennée
2022-03-04 14:16     ` Jonathan Cameron
2022-03-04 14:26       ` Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 23/43] hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142) Jonathan Cameron
2022-03-02 10:20   ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 24/43] acpi/cxl: Add _OSC implementation (9.14.2) Jonathan Cameron
2022-03-02 12:14   ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 25/43] acpi/cxl: Create the CEDT (9.14.1) Jonathan Cameron
2022-03-02 12:16   ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 26/43] hw/cxl/component: Add utils for interleave parameter encoding/decoding Jonathan Cameron
2022-03-02 12:17   ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 27/43] hw/cxl/host: Add support for CXL Fixed Memory Windows Jonathan Cameron
2022-03-02  6:55   ` Markus Armbruster
2022-03-04 15:56     ` Jonathan Cameron
2022-03-04 17:13       ` Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 28/43] acpi/cxl: Introduce CFMWS structures in CEDT Jonathan Cameron
2022-03-02 12:18   ` Alex Bennée
2022-02-11 12:07 ` Jonathan Cameron [this message]
2022-03-02 13:53   ` [PATCH v6 29/43] hw/pci-host/gpex-acpi: Add support for dsdt construction for pxb-cxl Alex Bennée
2022-02-11 12:07 ` [PATCH v6 30/43] pci/pcie_port: Add pci_find_port_by_pn() Jonathan Cameron
2022-03-02 16:07   ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 31/43] CXL/cxl_component: Add cxl_get_hb_cstate() Jonathan Cameron
2022-03-02 16:07   ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 32/43] mem/cxl_type3: Add read and write functions for associated hostmem Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 33/43] cxl/cxl-host: Add memops for CFMWS region Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 34/43] RFC: softmmu/memory: Add ops to memory_region_ram_init_from_file Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 35/43] hw/cxl/component Add a dumb HDM decoder handler Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 36/43] i386/pc: Enable CXL fixed memory windows Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 37/43] tests/acpi: q35: Allow addition of a CXL test Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 38/43] qtests/bios-tables-test: Add a test for CXL emulation Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 39/43] tests/acpi: Add tables " Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 40/43] qtest/cxl: Add more complex test cases with CFMWs Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 41/43] hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxl Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 42/43] qtest/cxl: Add aarch64 virt test for CXL Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 43/43] docs/cxl: Add initial Compute eXpress Link (CXL) documentation Jonathan Cameron
2022-02-18 18:17 ` [PATCH v6 00/43] CXl 2.0 emulation Support Jonathan Cameron

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20220211120747.3074-30-Jonathan.Cameron@huawei.com \
    --to=jonathan.cameron@huawei.com \
    --cc=alex.bennee@linaro.org \
    --cc=ben.widawsky@intel.com \
    --cc=cbrowy@avery-design.com \
    --cc=dan.j.williams@intel.com \
    --cc=f4bug@amsat.org \
    --cc=imammedo@redhat.com \
    --cc=linux-cxl@vger.kernel.org \
    --cc=linuxarm@huawei.com \
    --cc=marcel@redhat.com \
    --cc=mst@redhat.com \
    --cc=peter.maydell@linaro.org \
    --cc=qemu-devel@nongnu.org \
    --cc=samarths@cadence.com \
    --cc=saransh@ibm.com \
    --cc=shameerali.kolothum.thodi@huawei.com \
    --cc=shreyas.shah@elastics.cloud \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox