From: Ben Widawsky <ben.widawsky@intel.com>
To: Dan Williams <dan.j.williams@intel.com>
Cc: linux-cxl@vger.kernel.org, ira.weiny@intel.com,
vishal.l.verma@intel.com, alison.schofield@intel.com
Subject: Re: [PATCH v2 2/6] cxl/pci: Add debug for DVSEC range init failures
Date: Thu, 17 Mar 2022 10:36:39 -0700 [thread overview]
Message-ID: <20220317173639.b4tewk7hp4fr3jms@intel.com> (raw)
In-Reply-To: <164730734812.3806189.2726330688692684104.stgit@dwillia2-desk3.amr.corp.intel.com>
On 22-03-14 18:22:28, Dan Williams wrote:
> In preparation for not treating DVSEC range initialization failures as
> fatal to cxl_pci_probe() add individual dev_dbg() statements for each of
> the major failure reasons in cxl_dvsec_ranges().
>
> The rationale for cxl_dvsec_ranges() failure not being fatal is that
> there is still value for cxl_pci to enable mailbox operations even if
> CXL.mem operation is disabled.
>
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
> ---
> drivers/cxl/pci.c | 13 ++++++++++---
> 1 file changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index 8a7267d116b7..257cf735505d 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -467,12 +467,15 @@ static int cxl_dvsec_ranges(struct cxl_dev_state *cxlds)
> {
> struct cxl_endpoint_dvsec_info *info = &cxlds->info;
> struct pci_dev *pdev = to_pci_dev(cxlds->dev);
> + struct device *dev = &pdev->dev;
> int d = cxlds->cxl_dvsec;
> int hdm_count, rc, i;
> u16 cap, ctrl;
>
> - if (!d)
> + if (!d) {
> + dev_dbg(dev, "No DVSEC Capability\n");
> return -ENXIO;
> + }
>
> rc = pci_read_config_word(pdev, d + CXL_DVSEC_CAP_OFFSET, &cap);
> if (rc)
> @@ -482,8 +485,10 @@ static int cxl_dvsec_ranges(struct cxl_dev_state *cxlds)
> if (rc)
> return rc;
>
> - if (!(cap & CXL_DVSEC_MEM_CAPABLE))
> + if (!(cap & CXL_DVSEC_MEM_CAPABLE)) {
> + dev_dbg(dev, "Not MEM Capable\n");
> return -ENXIO;
> + }
>
> /*
> * It is not allowed by spec for MEM.capable to be set and have 0 legacy
> @@ -496,8 +501,10 @@ static int cxl_dvsec_ranges(struct cxl_dev_state *cxlds)
> return -EINVAL;
>
> rc = wait_for_valid(cxlds);
> - if (rc)
> + if (rc) {
> + dev_dbg(dev, "Failure awaiting MEM_INFO_VALID (%d)\n", rc);
> return rc;
> + }
>
> info->mem_enabled = FIELD_GET(CXL_DVSEC_MEM_ENABLE, ctrl);
>
>
It kind of stinks now that this function has some pdev->dev usages and plain dev
usages now. Either way, it's correct and an improvement.
Reviewed-by: Ben Widawsky <ben.widawsky@intel.com>
next prev parent reply other threads:[~2022-03-17 17:37 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-15 1:22 [PATCH v2 0/6] cxl: Handle DVSEC range init failures Dan Williams
2022-03-15 1:22 ` [PATCH v2 1/6] cxl/mem: Drop DVSEC vs EFI Memory Map sanity check Dan Williams
2022-03-17 17:33 ` Ben Widawsky
2022-03-25 11:34 ` Jonathan Cameron
2022-03-15 1:22 ` [PATCH v2 2/6] cxl/pci: Add debug for DVSEC range init failures Dan Williams
2022-03-17 17:36 ` Ben Widawsky [this message]
2022-03-25 11:38 ` Jonathan Cameron
2022-03-15 1:22 ` [PATCH v2 3/6] cxl/mem: Make cxl_dvsec_range() init failure fatal Dan Williams
2022-03-16 2:00 ` Davidlohr Bueso
2022-03-16 2:14 ` Dan Williams
2022-03-17 17:49 ` Ben Widawsky
2022-03-25 11:39 ` Jonathan Cameron
2022-03-15 1:22 ` [PATCH v2 4/6] cxl/pci: Make cxl_dvsec_ranges() failure not fatal to cxl_pci Dan Williams
2022-03-17 17:52 ` Ben Widawsky
2022-03-17 18:20 ` Dan Williams
2022-03-17 18:29 ` Ben Widawsky
2022-03-17 18:30 ` Dan Williams
2022-03-25 11:47 ` Jonathan Cameron
2022-03-15 1:22 ` [PATCH v2 5/6] cxl/mem: Rename cxl_dvsec_decode_init() to cxl_hdm_decode_init() Dan Williams
2022-03-17 17:54 ` Ben Widawsky
2022-03-17 18:45 ` Dan Williams
2022-03-25 11:50 ` Jonathan Cameron
2022-03-15 1:22 ` [PATCH v2 6/6] cxl/mem: Replace redundant debug message with a comment Dan Williams
2022-03-25 11:54 ` Jonathan Cameron
2022-04-08 19:30 ` [PATCH v3 " Dan Williams
2022-03-17 0:39 ` [PATCH v2 0/6] cxl: Handle DVSEC range init failures Davidlohr Bueso
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