From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: Dan Williams <dan.j.williams@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <vishal.l.verma@intel.com>,
<ira.weiny@intel.com>, <alison.schofield@intel.com>,
<dave.jiang@intel.com>
Subject: Re: [PATCH v2 2/3] cxl/region: Fix x1 interleave to greater than x1 interleave routing
Date: Tue, 9 Aug 2022 11:18:39 +0100 [thread overview]
Message-ID: <20220809111839.00003b43@huawei.com> (raw)
In-Reply-To: <62f163e4227ea_1b3c2945@dwillia2-xfh.jf.intel.com.notmuch>
On Mon, 8 Aug 2022 12:28:36 -0700
Dan Williams <dan.j.williams@intel.com> wrote:
> Jonathan Cameron wrote:
> > On Fri, 05 Aug 2022 13:27:45 -0700
> > Dan Williams <dan.j.williams@intel.com> wrote:
> >
> > > In cases where the decode fans out as it traverses downstream, the
> > > interleave granularity needs to increment to identify the port selector
> > > bits out of the remaining address bits. For example, recall that with an
> > > x2 parent port intereleave (IW == 1), the downstream decode for children
> > > of those ports will either see address bit IG+8 always set, or address
> > > bit IG+8 always clear. So if the child port needs to select a downstream
> > > port it can only use address bits starting at IG+9 (where IG and IW are
> > > the CXL encoded values for interleave granularity (ilog2(ig) - 8) and
> > > ways (ilog2(iw))).
> > >
> > > When the parent port interleave is x1 no such masking occurs and the
> > > child port can maintain the granularity that was routed to the parent
> > > port.
> > >
> > > Reported-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > > Signed-off-by: Dan Williams <dan.j.williams@intel.com>
> > Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > Tested-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> #via qemu
>
> Thanks Jonathan.
>
> In the interests of being able to make a:
>
> "these commits have appeared in Linux next with no known outstanding
> issues"
>
> ...I'd like to note these review and test tags in the merge message.
> They will still be in the history just not in the commits directly.
> Similar to what I did here:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/nvdimm/nvdimm.git/tag/?h=libnvdimm-for-5.17
>
> The current state of cxl/next hit linux-next last night. Let me know if
> you have any heartburn about that.
Fine by me.
I normally don't even do that if I'm rushing something in. Just rely on
the link to the thread in the actual patch description for anyone who cares.
Maybe I'll start doing something like you are, though can be a pain to gather them
up on a large pull request.
Jonathan
>
> > Now this is resolved, I'll get qemu fix sent out (hopefully later today).
>
> Good to hear, thanks.
next prev parent reply other threads:[~2022-08-09 10:18 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-05 20:27 [PATCH v2 0/3] CXL Region Provisioning Fixes Dan Williams
2022-08-05 20:27 ` [PATCH v2 1/3] cxl/region: Move HPA setup to cxl_region_attach() Dan Williams
2022-08-05 22:48 ` Ira Weiny
2022-08-08 11:04 ` Jonathan Cameron
2022-08-05 20:27 ` [PATCH v2 2/3] cxl/region: Fix x1 interleave to greater than x1 interleave routing Dan Williams
2022-08-05 21:54 ` Verma, Vishal L
2022-08-05 22:50 ` Ira Weiny
2022-08-08 11:03 ` Jonathan Cameron
2022-08-08 19:28 ` Dan Williams
2022-08-09 10:18 ` Jonathan Cameron [this message]
2022-08-05 20:27 ` [PATCH v2 3/3] cxl/region: Disallow region granularity != window granularity Dan Williams
2022-08-05 22:54 ` Ira Weiny
2022-08-08 11:24 ` Jonathan Cameron
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