Re: [PATCH v2 2/3] cxl/region: Fix x1 interleave to greater than x1 interleave routing

[Ira Weiny <ira.weiny@intel.com>]

On Fri, Aug 05, 2022 at 01:27:45PM -0700, Dan Williams wrote:
> In cases where the decode fans out as it traverses downstream, the
> interleave granularity needs to increment to identify the port selector
> bits out of the remaining address bits. For example, recall that with an
> x2 parent port intereleave (IW == 1), the downstream decode for children
> of those ports will either see address bit IG+8 always set, or address
> bit IG+8 always clear. So if the child port needs to select a downstream
> port it can only use address bits starting at IG+9 (where IG and IW are
> the CXL encoded values for interleave granularity (ilog2(ig) - 8) and
> ways (ilog2(iw))).
> 
> When the parent port interleave is x1 no such masking occurs and the
> child port can maintain the granularity that was routed to the parent
> port.
> 
> Reported-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>

Reviewed-by: Ira Weiny <ira.weiny@intel.com>

> ---
>  drivers/cxl/core/region.c |    6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> index e71077beb021..641bc6344a4a 100644
> --- a/drivers/cxl/core/region.c
> +++ b/drivers/cxl/core/region.c
> @@ -1025,7 +1025,11 @@ static int cxl_port_setup_targets(struct cxl_port *port,
>  		return rc;
>  	}
>  
> -	if (cxl_rr->nr_targets > 1) {
> +	/*
> +	 * If @parent_port is masking address bits, pick the next unused address
> +	 * bit to route @port's targets.
> +	 */
> +	if (parent_iw > 1 && cxl_rr->nr_targets > 1) {
>  		u32 address_bit = max(peig + peiw, eiw + peig);
>  
>  		eig = address_bit - eiw + 1;
>