From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: Dave Jiang <dave.jiang@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <alison.schofield@intel.com>,
<vishal.l.verma@intel.com>, <bwidawsk@kernel.org>,
<dan.j.williams@intel.com>, <shiju.jose@huawei.com>,
<rrichter@amd.com>
Subject: Re: [PATCH RFC v2 3/9] cxl/pci: Kill cxl_map_regs()
Date: Tue, 18 Oct 2022 14:43:53 +0100 [thread overview]
Message-ID: <20221018144353.00003339@huawei.com> (raw)
In-Reply-To: <166336987163.3803215.16274917380401720231.stgit@djiang5-desk3.ch.intel.com>
On Fri, 16 Sep 2022 16:11:11 -0700
Dave Jiang <dave.jiang@intel.com> wrote:
> From: Dan Williams <dan.j.williams@intel.com>
>
> The component registers are currently unused by the cxl_pci driver.
> Only the physical address base of the component registers is conveyed to
> the cxl_mem driver. Just call cxl_map_device_registers() directly.
>
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
These first 3 impact the CPMU driver code. So I'd very much like
to have these at least upstream asap even if the rest takes a while
to follow.
Thanks,
Jonathan
> ---
> drivers/cxl/pci.c | 23 +----------------------
> 1 file changed, 1 insertion(+), 22 deletions(-)
>
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index faeb5d9d7a7a..82023cf0cdcf 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -347,27 +347,6 @@ static int cxl_probe_regs(struct pci_dev *pdev, struct cxl_register_map *map)
> return 0;
> }
>
> -static int cxl_map_regs(struct cxl_dev_state *cxlds, struct cxl_register_map *map)
> -{
> - struct device *dev = cxlds->dev;
> - struct pci_dev *pdev = to_pci_dev(dev);
> -
> - switch (map->reg_type) {
> - case CXL_REGLOC_RBI_COMPONENT:
> - cxl_map_component_regs(pdev, &cxlds->regs.component, map);
> - dev_dbg(dev, "Mapping component registers...\n");
> - break;
> - case CXL_REGLOC_RBI_MEMDEV:
> - cxl_map_device_regs(pdev, &cxlds->regs.device_regs, map);
> - dev_dbg(dev, "Probing device registers...\n");
> - break;
> - default:
> - break;
> - }
> -
> - return 0;
> -}
> -
> static int cxl_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
> struct cxl_register_map *map)
> {
> @@ -461,7 +440,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
> if (rc)
> return rc;
>
> - rc = cxl_map_regs(cxlds, &map);
> + rc = cxl_map_device_regs(pdev, &cxlds->regs.device_regs, &map);
> if (rc)
> return rc;
>
>
>
next prev parent reply other threads:[~2022-10-18 13:44 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-16 23:10 [PATCH RFC v2 0/9] cxl/pci: Add fundamental error handling Dave Jiang
2022-09-16 23:11 ` [PATCH RFC v2 1/9] cxl/pci: Cleanup repeated code in cxl_probe_regs() helpers Dave Jiang
2022-09-16 23:11 ` [PATCH RFC v2 2/9] cxl/pci: Cleanup cxl_map_device_regs() Dave Jiang
2022-09-16 23:11 ` [PATCH RFC v2 3/9] cxl/pci: Kill cxl_map_regs() Dave Jiang
2022-10-18 13:43 ` Jonathan Cameron [this message]
2022-09-16 23:11 ` [PATCH RFC v2 4/9] cxl/core/regs: Make cxl_map_{component, device}_regs() device generic Dave Jiang
2022-09-16 23:11 ` [PATCH RFC v2 5/9] cxl/port: Limit the port driver to just the HDM Decoder Capability Dave Jiang
2022-10-20 16:54 ` Jonathan Cameron
2022-09-16 23:11 ` [PATCH RFC v2 6/9] cxl/pci: Prepare for mapping RAS Capability Structure Dave Jiang
2022-09-16 23:11 ` [PATCH RFC v2 7/9] cxl/pci: Find and map the " Dave Jiang
2022-09-16 23:11 ` [PATCH RFC v2 8/9] cxl/pci: add tracepoint events for CXL RAS Dave Jiang
2022-10-20 17:02 ` Jonathan Cameron
2022-10-20 17:07 ` Dave Jiang
2022-10-20 17:52 ` Steven Rostedt
2022-09-16 23:11 ` [PATCH RFC v2 9/9] cxl/pci: Add (hopeful) error handling support Dave Jiang
2022-10-20 13:45 ` Jonathan Cameron
2022-10-20 14:50 ` Dave Jiang
2022-10-20 14:03 ` Jonathan Cameron
2022-10-20 14:57 ` Dave Jiang
2022-10-20 15:52 ` Jonathan Cameron
2022-10-20 16:06 ` Dave Jiang
2022-10-20 16:11 ` Jonathan Cameron
2022-10-11 14:17 ` [PATCH RFC v2 0/9] cxl/pci: Add fundamental error handling Jonathan Cameron
2022-10-11 15:18 ` Dave Jiang
2022-10-11 17:19 ` Jonathan Cameron
2022-10-19 17:30 ` Jonathan Cameron
2022-10-19 17:38 ` Dave Jiang
2022-10-24 16:01 ` Jonathan Cameron
2022-10-25 15:22 ` Dave Jiang
2022-11-03 12:58 ` Jonathan Cameron
2022-11-03 13:27 ` Jonathan Cameron
2022-11-16 23:20 ` Dave Jiang
2022-11-17 13:50 ` Jonathan Cameron
2022-11-18 17:15 ` Dave Jiang
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