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From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: Dave Jiang <dave.jiang@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <dan.j.williams@intel.com>,
	<ira.weiny@intel.com>, <vishal.l.verma@intel.com>,
	<alison.schofield@intel.com>
Subject: Re: [PATCH] cxl: update eiw_to_ways() comment referring to cxl spec
Date: Tue, 25 Oct 2022 12:06:24 +0100	[thread overview]
Message-ID: <20221025120624.00001516@huawei.com> (raw)
In-Reply-To: <166664850753.511468.15931290944330812647.stgit@djiang5-desk3.ch.intel.com>

On Mon, 24 Oct 2022 14:55:07 -0700
Dave Jiang <dave.jiang@intel.com> wrote:

> Change comment pointing to CLX ECN to the releveant released rev3 spec.
> 
> Suggested-by: Alison Schofield <alison.schofield@intel.com>
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Confirmed reference is correct.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

> ---
>  drivers/cxl/cxl.h |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index e2a1a7523a2b..512ba28a6349 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -77,7 +77,7 @@ static inline int eig_to_granularity(u16 eig, unsigned int *granularity)
>  	return 0;
>  }
>  
> -/* Encode defined in CXL ECN "3, 6, 12 and 16-way memory Interleaving" */
> +/* Encode defined in CXL rev3.0 8.2.4.19.7 CXL HDM Decoder n Control Register */
>  static inline int eiw_to_ways(u8 eiw, unsigned int *ways)
>  {
>  	switch (eiw) {
> 
> 


      reply	other threads:[~2022-10-25 11:06 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-24 21:55 [PATCH] cxl: update eiw_to_ways() comment referring to cxl spec Dave Jiang
2022-10-25 11:06 ` Jonathan Cameron [this message]

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