Re: Prototyping on CXL hardware

[Jonathan Cameron <Jonathan.Cameron@Huawei.com>]

On Tue, 22 Nov 2022 10:54:52 +0100
Julien BERAUD <jberaud@sasfermat.com> wrote:

> Hello Everyone,
> 

Hi Julien, Nice to 'meet' you.

> I'm currently trying to prototype with a simple use-case on a CXL type 3 device
> directly connected to a CXL 2.0 capable server.
> 
> Since I have seen many patches being integrated in the mainline kernel, I am 
> running a 6.0.1 release.
> 
> The init phase of the drivers fails with the following trace:
> 
> cxl_mem mem0: at mem0 no parent for dport: pci0000:16
> 
> It occurs at the first iteration of the loop in devm_cxl_enumerate_ports 
> 
> The previous steps have been succeding as far as I know.
> 
> ---------------------------------------------------------------------------------
> So I have a few questions that I hope someone can answer here, I am sorry if they
> sound naive :
> 
> - What is supposed to fill the device's ancestry, and what does it means if there
> is none ?
> 
> - More generally, is a CXL type 3 device directly connected to a CXL capable
> server supposed to initialize correctly on a 6.0.1 kernel or should I use a more
> advanced branch ?

To take a lazy punt in the dark as it end of day here.

Do you have an ACPI CEDT table and required ACPI stuff such as ACPI0017 in DSDT?
Otherwise the root of the created CXL topology will be missing - I haven't checked
the code paths, but that might well give the above result.

There are a few fixes you will want on top of 6.0.1 - but those are all around
region creation I think, so you aren't getting that far.
I've not been tracking progress of those. Dan, what's the current status?

For reference you could take a look at the upstream QEMU (very recent needed as we
had a fix going through on x86).  That should work and gives you something to compare
with when bringing up real hardware.

Jonathan

> 
> 
> Thanks in advance for your answers,
> Julien