Prototyping on CXL hardware

[Julien BERAUD <jberaud@sasfermat.com>]

Hello Everyone,

I'm currently trying to prototype with a simple use-case on a CXL type 3 device
directly connected to a CXL 2.0 capable server.

Since I have seen many patches being integrated in the mainline kernel, I am 
running a 6.0.1 release.

The init phase of the drivers fails with the following trace:

cxl_mem mem0: at mem0 no parent for dport: pci0000:16

It occurs at the first iteration of the loop in devm_cxl_enumerate_ports 

The previous steps have been succeding as far as I know.

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So I have a few questions that I hope someone can answer here, I am sorry if they
sound naive :

- What is supposed to fill the device's ancestry, and what does it means if there
is none ?

- More generally, is a CXL type 3 device directly connected to a CXL capable
server supposed to initialize correctly on a 6.0.1 kernel or should I use a more
advanced branch ?


Thanks in advance for your answers,
Julien