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From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Ira Weiny <ira.weiny@intel.com>
Cc: Dan Williams <dan.j.williams@intel.com>,
	<linux-cxl@vger.kernel.org>, Dave Jiang <dave.jiang@intel.com>
Subject: Re: [PATCH] cxl/pci: Remove endian confusion
Date: Tue, 6 Dec 2022 09:50:29 +0000	[thread overview]
Message-ID: <20221206095029.000069d5@Huawei.com> (raw)
In-Reply-To: <Y47knR08oCyC+uxO@iweiny-desk3>

On Mon, 5 Dec 2022 22:43:41 -0800
Ira Weiny <ira.weiny@intel.com> wrote:

> On Mon, Dec 05, 2022 at 08:28:40PM -0800, Dan Williams wrote:
> > readl() already handles endian conversion. That's the main difference
> > between readl() and __raw_readl(). This is benign on little-endian
> > systems, but big endian systems will end up byte-swabbing twice.
> > 
> > Fixes: 2905cb5236cb ("cxl/pci: Add (hopeful) error handling support")
> > Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > Cc: Dave Jiang <dave.jiang@intel.com>  
> 
> Reviewed-by: Ira Weiny <ira.weiny@intel.com>

Gah. Hate endian mess.  Anyone actually want big endian support? :)

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

> 
> > Signed-off-by: Dan Williams <dan.j.williams@intel.com>
> > ---
> >  drivers/cxl/pci.c |    7 +++----
> >  1 file changed, 3 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> > index cced4a0df3d1..33083a522fd1 100644
> > --- a/drivers/cxl/pci.c
> > +++ b/drivers/cxl/pci.c
> > @@ -548,15 +548,14 @@ static bool cxl_report_and_clear(struct cxl_dev_state *cxlds)
> >  		return false;
> >  
> >  	addr = cxlds->regs.ras + CXL_RAS_UNCORRECTABLE_STATUS_OFFSET;
> > -	status = le32_to_cpu((__force __le32)readl(addr));
> > +	status = readl(addr);
> >  	if (!(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK))
> >  		return false;
> >  
> >  	/* If multiple errors, log header points to first error from ctrl reg */
> >  	if (hweight32(status) > 1) {
> >  		addr = cxlds->regs.ras + CXL_RAS_CAP_CONTROL_OFFSET;
> > -		fe = BIT(le32_to_cpu((__force __le32)readl(addr)) &
> > -				     CXL_RAS_CAP_CONTROL_FE_MASK);
> > +		fe = BIT(FIELD_GET(CXL_RAS_CAP_CONTROL_FE_MASK, readl(addr)));
> >  	} else {
> >  		fe = status;
> >  	}
> > @@ -641,7 +640,7 @@ static void cxl_cor_error_detected(struct pci_dev *pdev)
> >  		return;
> >  
> >  	addr = cxlds->regs.ras + CXL_RAS_CORRECTABLE_STATUS_OFFSET;
> > -	status = le32_to_cpu(readl(addr));
> > +	status = readl(addr);
> >  	if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) {
> >  		writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr);
> >  		trace_cxl_aer_correctable_error(dev, status);
> >   


  reply	other threads:[~2022-12-06  9:52 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-06  4:28 [PATCH] cxl/pci: Remove endian confusion Dan Williams
2022-12-06  6:43 ` Ira Weiny
2022-12-06  9:50   ` Jonathan Cameron [this message]
2022-12-06 17:04 ` Dave Jiang
2022-12-07 17:01 ` Christoph Hellwig

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