From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Dave Jiang <dave.jiang@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <dan.j.williams@intel.com>,
<ira.weiny@intel.com>, <vishal.l.verma@intel.com>,
<alison.schofield@intel.com>, <rrichter@amd.com>,
<terry.bowman@amd.com>
Subject: Re: [RFC PATCH 7/8] cxl: suppress component register discovery failure warning for RCD
Date: Mon, 19 Dec 2022 17:35:10 +0000 [thread overview]
Message-ID: <20221219173510.000003ed@Huawei.com> (raw)
In-Reply-To: <166984997536.2805382.16376618769262720267.stgit@djiang5-desk3.ch.intel.com>
On Wed, 30 Nov 2022 16:12:55 -0700
Dave Jiang <dave.jiang@intel.com> wrote:
> For an RCD, it is expected that component register won't be discovered by
> cxl_pci. Suppress warning if RCD.
I've lost track a bit on where this ended up in the RCD series
but from a spec point of view 8.2.2 in CXL 3.0 makes it clear
that it's fine for component registers to be in a BAR and hence
the register block locator. Hence does the "expected" want relaxing
to an "allowed" or even "likely". Expected kind of implies the
opposite isn't expected.
>
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
> ---
> drivers/cxl/pci.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index 73ff6c33a0c0..d808da838909 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -486,7 +486,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
> */
> cxlds->component_reg_phys = CXL_RESOURCE_NONE;
> rc = cxl_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, &map);
> - if (rc)
> + if (rc && !cxlds->rcd)
> dev_warn(&pdev->dev, "No component registers (%d)\n", rc);
>
> cxlds->component_reg_phys = cxl_regmap_to_base(pdev, &map);
>
>
next prev parent reply other threads:[~2022-12-19 17:35 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-30 23:12 [RFC PATCH 0/8] cxl: Introduce HDM decoder emulation from DVSEC range registers Dave Jiang
2022-11-30 23:12 ` [RFC PATCH 1/8] cxl: break out range register decoding from cxl_hdm_decode_init() Dave Jiang
2022-12-19 15:59 ` Jonathan Cameron
2023-01-03 21:32 ` Dave Jiang
2022-11-30 23:12 ` [RFC PATCH 2/8] cxl: export cxl_dvsec_rr_decode() to cxl_port Dave Jiang
2022-12-19 16:11 ` Jonathan Cameron
2022-11-30 23:12 ` [RFC PATCH 3/8] cxl: refactor cxl_hdm_decode_init() Dave Jiang
2022-12-19 16:19 ` Jonathan Cameron
2022-11-30 23:12 ` [RFC PATCH 4/8] cxl: emulate HDM decoder from DVSEC range registers Dave Jiang
2022-12-19 16:42 ` Jonathan Cameron
2023-01-03 23:20 ` Dave Jiang
2023-01-04 16:07 ` Dave Jiang
2023-01-05 10:51 ` Jonathan Cameron
2022-11-30 23:12 ` [RFC PATCH 5/8] cxl: create emulated cxl_hdm for devices that do not have HDM decoders Dave Jiang
2022-12-19 16:52 ` Jonathan Cameron
2022-11-30 23:12 ` [RFC PATCH 6/8] cxl: create emulated decoders for devices without " Dave Jiang
2022-12-19 17:00 ` Jonathan Cameron
2022-11-30 23:12 ` [RFC PATCH 7/8] cxl: suppress component register discovery failure warning for RCD Dave Jiang
2022-12-19 17:35 ` Jonathan Cameron [this message]
2022-11-30 23:13 ` [RFC PATCH 8/8] cxl: remove locked check for dvsec_range_allowed() Dave Jiang
2022-12-19 16:12 ` [RFC PATCH 0/8] cxl: Introduce HDM decoder emulation from DVSEC range registers Jonathan Cameron
2022-12-19 16:19 ` Dave Jiang
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