* [PATCH] cxl: fix cxl_report_and_clear() RAS UE addr mis-assignment
@ 2023-01-06 16:39 Dave Jiang
2023-01-06 17:05 ` Ira Weiny
2023-01-09 14:19 ` Jonathan Cameron
0 siblings, 2 replies; 3+ messages in thread
From: Dave Jiang @ 2023-01-06 16:39 UTC (permalink / raw)
To: linux-cxl
Cc: dan.j.williams, ira.weiny, vishal.l.verma, alison.schofield,
jonathan.cameron
'addr' that contains RAS UE register address is re-assigned to
RAS_CAP_CONTROL offset if there are multiple UE errors. Use different addr
variable to avoid the reassignment mistake.
Fixes: 2905cb5236cb ("cxl/pci: Add (hopeful) error handling support")
Reported-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
---
drivers/cxl/pci.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index 33083a522fd1..258004f34281 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -554,8 +554,11 @@ static bool cxl_report_and_clear(struct cxl_dev_state *cxlds)
/* If multiple errors, log header points to first error from ctrl reg */
if (hweight32(status) > 1) {
- addr = cxlds->regs.ras + CXL_RAS_CAP_CONTROL_OFFSET;
- fe = BIT(FIELD_GET(CXL_RAS_CAP_CONTROL_FE_MASK, readl(addr)));
+ void __iomem *rcc_addr =
+ cxlds->regs.ras + CXL_RAS_CAP_CONTROL_OFFSET;
+
+ fe = BIT(FIELD_GET(CXL_RAS_CAP_CONTROL_FE_MASK,
+ readl(rcc_addr)));
} else {
fe = status;
}
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH] cxl: fix cxl_report_and_clear() RAS UE addr mis-assignment
2023-01-06 16:39 [PATCH] cxl: fix cxl_report_and_clear() RAS UE addr mis-assignment Dave Jiang
@ 2023-01-06 17:05 ` Ira Weiny
2023-01-09 14:19 ` Jonathan Cameron
1 sibling, 0 replies; 3+ messages in thread
From: Ira Weiny @ 2023-01-06 17:05 UTC (permalink / raw)
To: Dave Jiang
Cc: linux-cxl, dan.j.williams, vishal.l.verma, alison.schofield,
jonathan.cameron
On Fri, Jan 06, 2023 at 09:39:49AM -0700, Jiang, Dave wrote:
> 'addr' that contains RAS UE register address is re-assigned to
> RAS_CAP_CONTROL offset if there are multiple UE errors. Use different addr
> variable to avoid the reassignment mistake.
>
> Fixes: 2905cb5236cb ("cxl/pci: Add (hopeful) error handling support")
> Reported-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
> ---
> drivers/cxl/pci.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index 33083a522fd1..258004f34281 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -554,8 +554,11 @@ static bool cxl_report_and_clear(struct cxl_dev_state *cxlds)
>
> /* If multiple errors, log header points to first error from ctrl reg */
> if (hweight32(status) > 1) {
> - addr = cxlds->regs.ras + CXL_RAS_CAP_CONTROL_OFFSET;
> - fe = BIT(FIELD_GET(CXL_RAS_CAP_CONTROL_FE_MASK, readl(addr)));
> + void __iomem *rcc_addr =
> + cxlds->regs.ras + CXL_RAS_CAP_CONTROL_OFFSET;
> +
> + fe = BIT(FIELD_GET(CXL_RAS_CAP_CONTROL_FE_MASK,
> + readl(rcc_addr)));
> } else {
> fe = status;
> }
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH] cxl: fix cxl_report_and_clear() RAS UE addr mis-assignment
2023-01-06 16:39 [PATCH] cxl: fix cxl_report_and_clear() RAS UE addr mis-assignment Dave Jiang
2023-01-06 17:05 ` Ira Weiny
@ 2023-01-09 14:19 ` Jonathan Cameron
1 sibling, 0 replies; 3+ messages in thread
From: Jonathan Cameron @ 2023-01-09 14:19 UTC (permalink / raw)
To: Dave Jiang
Cc: linux-cxl, dan.j.williams, ira.weiny, vishal.l.verma,
alison.schofield
On Fri, 06 Jan 2023 09:39:49 -0700
Dave Jiang <dave.jiang@intel.com> wrote:
> 'addr' that contains RAS UE register address is re-assigned to
> RAS_CAP_CONTROL offset if there are multiple UE errors. Use different addr
> variable to avoid the reassignment mistake.
>
> Fixes: 2905cb5236cb ("cxl/pci: Add (hopeful) error handling support")
> Reported-by: Jonathan Cameron <jonathan.cameron@huawei.com>
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Exactly what I expected. Thanks for the quick turn around.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
I'm working on adding multiple header log handling on top of your
code. Will hopefully have something to share on that later in the week.
> ---
> drivers/cxl/pci.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index 33083a522fd1..258004f34281 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -554,8 +554,11 @@ static bool cxl_report_and_clear(struct cxl_dev_state *cxlds)
>
> /* If multiple errors, log header points to first error from ctrl reg */
> if (hweight32(status) > 1) {
> - addr = cxlds->regs.ras + CXL_RAS_CAP_CONTROL_OFFSET;
> - fe = BIT(FIELD_GET(CXL_RAS_CAP_CONTROL_FE_MASK, readl(addr)));
> + void __iomem *rcc_addr =
> + cxlds->regs.ras + CXL_RAS_CAP_CONTROL_OFFSET;
> +
> + fe = BIT(FIELD_GET(CXL_RAS_CAP_CONTROL_FE_MASK,
> + readl(rcc_addr)));
> } else {
> fe = status;
> }
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2023-01-09 14:19 UTC | newest]
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2023-01-06 16:39 [PATCH] cxl: fix cxl_report_and_clear() RAS UE addr mis-assignment Dave Jiang
2023-01-06 17:05 ` Ira Weiny
2023-01-09 14:19 ` Jonathan Cameron
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