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From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: "Philippe Mathieu-Daudé" <philmd@linaro.org>
Cc: <qemu-devel@nongnu.org>, Michael Tsirkin <mst@redhat.com>,
	Ben Widawsky <bwidawsk@kernel.org>, <linux-cxl@vger.kernel.org>,
	<linuxarm@huawei.com>, "Ira Weiny" <ira.weiny@intel.com>,
	Gregory Price <gourry.memverge@gmail.com>,
	Mike Maslenkin <mike.maslenkin@gmail.com>,
	Dave Jiang <dave.jiang@intel.com>,
	Markus Armbruster <armbru@redhat.com>
Subject: Re: [PATCH v5 8/8] hw/mem/cxl_type3: Add CXL RAS Error Injection Support.
Date: Wed, 22 Feb 2023 14:53:30 +0000	[thread overview]
Message-ID: <20230222145330.000021ef@huawei.com> (raw)
In-Reply-To: <e432cebc-8faa-7b41-71c8-ea88c7bcbb04@linaro.org>

On Tue, 21 Feb 2023 23:15:49 +0100
Philippe Mathieu-Daudé <philmd@linaro.org> wrote:

> Hi Jonathan,
> 
> On 21/2/23 16:21, Jonathan Cameron wrote:
> > CXL uses PCI AER Internal errors to signal to the host that an error has
> > occurred. The host can then read more detailed status from the CXL RAS
> > capability.
> > 
> > For uncorrectable errors: support multiple injection in one operation
> > as this is needed to reliably test multiple header logging support in an
> > OS. The equivalent feature doesn't exist for correctable errors, so only
> > one error need be injected at a time.
> > 
> > Note:
> >   - Header content needs to be manually specified in a fashion that
> >     matches the specification for what can be in the header for each
> >     error type.
> > 
> > Injection via QMP:
> > { "execute": "qmp_capabilities" }
> > ...
> > { "execute": "cxl-inject-uncorrectable-errors",
> >    "arguments": {
> >      "path": "/machine/peripheral/cxl-pmem0",
> >      "errors": [
> >          {
> >              "type": "cache-address-parity",
> >              "header": [ 3, 4]
> >          },
> >          {
> >              "type": "cache-data-parity",
> >              "header": [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31]
> >          },
> >          {
> >              "type": "internal",
> >              "header": [ 1, 2, 4]
> >          }
> >          ]
> >    }}
> > ...
> > { "execute": "cxl-inject-correctable-error",
> >      "arguments": {
> >          "path": "/machine/peripheral/cxl-pmem0",
> >          "type": "physical"
> >      } }
> > 
> > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

Hi Philippe,

Thanks for your review.  One question inline.

> > +#
> > +# Type of uncorrectable CXL error to inject. These errors are reported via
> > +# an AER uncorrectable internal error with additional information logged at
> > +# the CXL device.
> > +#
> > +# @cache-data-parity: Data error such as data parity or data ECC error CXL.cache
> > +# @cache-address-parity: Address parity or other errors associated with the
> > +#                        address field on CXL.cache
> > +# @cache-be-parity: Byte enable parity or other byte enable errors on CXL.cache
> > +# @cache-data-ecc: ECC error on CXL.cache
> > +# @mem-data-parity: Data error such as data parity or data ECC error on CXL.mem
> > +# @mem-address-parity: Address parity or other errors associated with the
> > +#                      address field on CXL.mem
> > +# @mem-be-parity: Byte enable parity or other byte enable errors on CXL.mem.
> > +# @mem-data-ecc: Data ECC error on CXL.mem.
> > +# @reinit-threshold: REINIT threshold hit.
> > +# @rsvd-encoding: Received unrecognized encoding.
> > +# @poison-received: Received poison from the peer.
> > +# @receiver-overflow: Buffer overflows (first 3 bits of header log indicate which)
> > +# @internal: Component specific error
> > +# @cxl-ide-tx: Integrity and data encryption tx error.
> > +# @cxl-ide-rx: Integrity and data encryption rx error.
> > +##
> > +
> > +{ 'enum': 'CxlUncorErrorType',  
> 
> Doesn't these need
> 
>       'if': 'CONFIG_CXL_MEM_DEVICE',
> 
> ?

If I make this change I get a bunch of

./qapi/qapi-types-cxl.h:18:13: error: attempt to use poisoned "CONFIG_CXL_MEM_DEVICE"
   18 | #if defined(CONFIG_CXL_MEM_DEVICE)

It's a target specific define (I think) as built alongside PCI_EXPRESS
Only CXL_ACPI is specifically included by x86 and arm64 (out of tree)

To be honest though I don't fully understand the QEMU build system so the reason
for the error might be wrong.

> 
> > +  'data': ['cache-data-parity',
> > +           'cache-address-parity',
> > +           'cache-be-parity',
> > +           'cache-data-ecc',
> > +           'mem-data-parity',
> > +           'mem-address-parity',
> > +           'mem-be-parity',
> > +           'mem-data-ecc',
> > +           'reinit-threshold',
> > +           'rsvd-encoding',
> > +           'poison-received',
> > +           'receiver-overflow',
> > +           'internal',
> > +           'cxl-ide-tx',
> > +           'cxl-ide-rx'
> > +           ]
> > + }

  reply	other threads:[~2023-02-22 14:53 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-02-21 15:21 [PATCH v5 0/8] hw/cxl: RAS error emulation and injection Jonathan Cameron
2023-02-21 15:21 ` [PATCH v5 1/8] hw/pci/aer: Implement PCI_ERR_UNCOR_MASK register Jonathan Cameron
2023-02-21 15:21 ` [PATCH v5 2/8] hw/pci/aer: Add missing routing for AER errors Jonathan Cameron
2023-02-21 15:21 ` [PATCH v5 3/8] hw/pci-bridge/cxl_root_port: Wire up AER Jonathan Cameron
2023-02-21 15:21 ` [PATCH v5 4/8] hw/pci-bridge/cxl_root_port: Wire up MSI Jonathan Cameron
2023-02-21 15:21 ` [PATCH v5 5/8] hw/mem/cxl-type3: Add AER extended capability Jonathan Cameron
2023-02-21 15:21 ` [PATCH v5 6/8] hw/cxl: Fix endian issues in CXL RAS capability defaults / masks Jonathan Cameron
2023-02-21 22:06   ` Philippe Mathieu-Daudé
2023-02-21 15:21 ` [PATCH v5 7/8] hw/pci/aer: Make PCIE AER error injection facility available for other emulation to use Jonathan Cameron
2023-02-21 22:08   ` Philippe Mathieu-Daudé
2023-02-21 15:21 ` [PATCH v5 8/8] hw/mem/cxl_type3: Add CXL RAS Error Injection Support Jonathan Cameron
2023-02-21 15:48   ` Dave Jiang
2023-02-21 22:15   ` Philippe Mathieu-Daudé
2023-02-22 14:53     ` Jonathan Cameron [this message]
2023-02-22 15:32       ` Philippe Mathieu-Daudé
2023-02-22 16:49         ` Jonathan Cameron
2023-02-22 18:16           ` Philippe Mathieu-Daudé
2023-02-23  6:58             ` Thomas Huth
2023-02-23  7:37               ` Markus Armbruster
2023-02-23 14:27                 ` Jonathan Cameron
2023-02-24 17:37                   ` Jonathan Cameron
2023-02-24 19:02                   ` Philippe Mathieu-Daudé
2023-02-27  9:40                     ` Markus Armbruster
2023-02-22 18:28       ` Markus Armbruster
2023-10-27  4:54   ` Markus Armbruster
2023-10-31 17:55     ` Jonathan Cameron
2023-11-02  6:47       ` Markus Armbruster

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