Re: [PATCH 2/3] cxl/mbox: Wire up interrupts for background completion

[Jonathan Cameron <Jonathan.Cameron@Huawei.com>]

On Tue, 11 Apr 2023 19:22:44 -0700
Davidlohr Bueso <dave@stgolabs.net> wrote:

> On Mon, 03 Apr 2023, Jonathan Cameron wrote:
> 
> >Also, the interrupt setup for the PCI cap is missing I think.
> >See handling in ct3_realize()  
> 
> Hmm how is this any different that what is already there
> for events and cpmu? Once msi is initialized for the device,
> I didn't expect any other setup necessary - and I'm also
> receiving irqs fine with this patch at the driver side.

Ah. Seems you are sharing with the DOE for the compliance
mailbox - probably not the intent but as we have no code
that binds to that at the moment I guess you won't notice
the sharing.  It should be harmless but I'd put this on 11
and increase msix_num in ct3_realize.

At somepoint I need to make all the msix code for all usecase
deal with the OS asking for fewer vectors.  Not a problem with
Linux as it always grabs them all, but the emulation isn't currently
spec compliant as those numbers should 'squish' into the available
space if not enough is requested.

When that's not happening I should add an enum for msix vectors
so that we can more easily reorder the patches that add them.

Jonathan


> 
> Thanks,
> Davidlohr