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From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Dave Jiang <dave.jiang@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <dan.j.williams@intel.com>,
	<ira.weiny@intel.com>, <vishal.l.verma@intel.com>,
	<alison.schofield@intel.com>
Subject: Re: [PATCH v6 01/11] cxl: Add callback to parse the DSMAS subtables from CDAT
Date: Thu, 25 May 2023 17:43:12 +0100	[thread overview]
Message-ID: <20230525174312.00007fb2@Huawei.com> (raw)
In-Reply-To: <168451600072.3470703.11316174773607021145.stgit@djiang5-mobl3>

On Fri, 19 May 2023 10:06:40 -0700
Dave Jiang <dave.jiang@intel.com> wrote:

> Provide a callback function to the CDAT parser in order to parse the Device
> Scoped Memory Affinity Structure (DSMAS). Each DSMAS structure contains the
> DPA range and its associated attributes in each entry. See the CDAT
> specification for details. The device handle and the DPA range is saved and
> to be associated with the DSLBIS locality data when the DSLBIS entries are
> parsed. The list is a local list. When the total path performance data is
> calculated and storred this list can be discarded.
> 
> Coherent Device Attribute Table 1.03 2.1 Device Scoped memory Affinity
> Structure (DSMAS)
> 
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
One trivial comment inline.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

> diff --git a/drivers/cxl/core/cdat.c b/drivers/cxl/core/cdat.c
> new file mode 100644
> index 000000000000..f70a3a146901
> --- /dev/null
> +++ b/drivers/cxl/core/cdat.c
> @@ -0,0 +1,58 @@
...

> +void cxl_cdat_dsmas_list_destroy(struct list_head *dsmas_list)
> +{
> +	struct dsmas_entry *dentry, *n;
> +
> +	list_for_each_entry_safe(dentry, n, dsmas_list, list) {
> +		list_del(&dentry->list);
> +		kfree(dentry);
> +	}
> +}
> +EXPORT_SYMBOL_NS_GPL(cxl_cdat_dsmas_list_destroy, CXL);
> +
> +MODULE_IMPORT_NS(CXL);
> +

Trivial: Stray line at end of file?

> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h



  reply	other threads:[~2023-05-25 16:43 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-19 17:06 [PATCH v6 00/11] cxl: Add support for QTG ID retrieval for CXL subsystem Dave Jiang
2023-05-19 17:06 ` [PATCH v6 01/11] cxl: Add callback to parse the DSMAS subtables from CDAT Dave Jiang
2023-05-25 16:43   ` Jonathan Cameron [this message]
2023-05-19 17:06 ` [PATCH v6 02/11] cxl: Add callback to parse the DSLBIS subtable " Dave Jiang
2023-05-19 17:06 ` [PATCH v6 03/11] cxl: Add callback to parse the SSLBIS " Dave Jiang
2023-05-19 17:06 ` [PATCH v6 04/11] cxl: Add support for _DSM Function for retrieving QTG ID Dave Jiang
2023-05-25 16:44   ` Jonathan Cameron
2023-05-25 21:09     ` Dave Jiang
2023-05-19 17:07 ` [PATCH v6 05/11] cxl: Calculate and store PCI link latency for the downstream ports Dave Jiang
2023-05-19 17:07 ` [PATCH v6 06/11] cxl: Store the access coordinates for the generic ports Dave Jiang
2023-06-01 14:20   ` Jonathan Cameron
2023-05-19 17:07 ` [PATCH v6 07/11] cxl: Add helper function that calculate performance data for downstream ports Dave Jiang
2023-05-19 17:07 ` [PATCH v6 08/11] cxl: Compute the entire CXL path latency and bandwidth data Dave Jiang
2023-05-19 17:07 ` [PATCH v6 09/11] cxl: Store QTG IDs and related info to the CXL memory device context Dave Jiang
2023-06-01 14:32   ` Jonathan Cameron
2023-05-19 17:07 ` [PATCH v6 10/11] cxl: Export sysfs attributes for memory device QoS class Dave Jiang
2023-06-01 14:30   ` Jonathan Cameron
2023-06-01 17:13     ` Dave Jiang
2023-05-19 17:07 ` [PATCH v6 11/11] cxl/mem: Add debugfs output for QTG related data Dave Jiang

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