From: Dave Jiang <dave.jiang@intel.com>
To: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
Cc: <linux-cxl@vger.kernel.org>,
Dan Williams <dan.j.williams@intel.com>, <ira.weiny@intel.com>,
<vishal.l.verma@intel.com>, <alison.schofield@intel.com>
Subject: Re: [PATCH v6 10/11] cxl: Export sysfs attributes for memory device QoS class
Date: Thu, 1 Jun 2023 10:13:26 -0700 [thread overview]
Message-ID: <8081b4a3-8c86-5b6b-e972-a09eb98367c2@intel.com> (raw)
In-Reply-To: <20230601153021.000022bd@Huawei.com>
On 6/1/23 07:30, Jonathan Cameron wrote:
> On Fri, 19 May 2023 10:07:34 -0700
> Dave Jiang <dave.jiang@intel.com> wrote:
>
>> Export qos_class sysfs attributes for the CXL memory device. The QoS clas
>> should show up as /sys/bus/cxl/devices/memX/ram/qos_class for the volatile
>> partition and /sys/bus/cxl/devices/memX/pmem/qos_class for the persistent
>> partition. The QTG ID is retrieved via _DSM after supplying the
>> calculated bandwidth and latency for the entire CXL path from device to
>> the CPU. This ID is used to match up to the root decoder QoS class to
>> determine which CFMWS the memory range of a hotplugged CXL mem device
>> should be assigned under.
>>
>> While there may be multiple DSMAS exported by the device CDAT, the driver
>> will only expose the first QTG ID per partition in sysfs for now. In the
>> future when multiple QTG IDs are necessary, they can be exposed. [1]
>>
>> [1]: https://lore.kernel.org/linux-cxl/167571650007.587790.10040913293130712882.stgit@djiang5-mobl3.local/T/#md2a47b1ead3e1ba08f50eab29a4af1aed1d215ab
>>
>> Suggested-by: Dan Williams <dan.j.williams@intel.com>
>> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
> A few minor suggestions inline.
> In particular some code duplication that looks easy to avoid.
>
> Jonathan
>
>> ---
>> v6:
>> - Provide full ordered QTG IDs from _DSM. (Jonathan)
>> v5:
>> - Change qtg_id to qos_class
>> v4:
>> - Change kernel version for documentation to v6.5
>> v3:
>> - Expand description of qtg_id. (Alison)
>> ---
>> Documentation/ABI/testing/sysfs-bus-cxl | 34 +++++++++++++++++++
>> drivers/cxl/core/memdev.c | 55 +++++++++++++++++++++++++++++++
>> 2 files changed, 89 insertions(+)
>>
>> diff --git a/Documentation/ABI/testing/sysfs-bus-cxl b/Documentation/ABI/testing/sysfs-bus-cxl
>> index ccfc7ecc61f5..7a4cacd382f9 100644
>> --- a/Documentation/ABI/testing/sysfs-bus-cxl
>> +++ b/Documentation/ABI/testing/sysfs-bus-cxl
>> @@ -28,6 +28,23 @@ Description:
>> Payload in the CXL-2.0 specification.
>>
>>
>> +What: /sys/bus/cxl/devices/memX/ram/qos_class
>> +Date: May, 2023
>> +KernelVersion: v6.5
>> +Contact: linux-cxl@vger.kernel.org
>> +Description:
>> + (RO) For CXL host platforms that support "QoS Telemmetry"
>> + this attribute conveys a comma delimited list of platform
>> + specific cookies that identifies a QoS performance class
>> + for the volatile partition of the CXL mem device. These
>> + class-ids can be compared against a similar "qos_class"
>> + published for a root decoder. While it is not required
>> + that the endpoints map their local memory-class to a
>> + matching platform class, mismatches are not recommended
>> + and there are platform specific side-effects that may
>> + result.
> That sounds scary - perhaps "platform specific performance related
> side-effects that may result."
Ok will update
>> +
>> +
>> What: /sys/bus/cxl/devices/memX/pmem/size
>> Date: December, 2020
>> KernelVersion: v5.12
>> @@ -38,6 +55,23 @@ Description:
>> Payload in the CXL-2.0 specification.
>>
>>
>> +What: /sys/bus/cxl/devices/memX/pmem/qos_class
>> +Date: May, 2023
>> +KernelVersion: v6.5
>> +Contact: linux-cxl@vger.kernel.org
>> +Description:
>> + (RO) For CXL host platforms that support "QoS Telemmetry"
>> + this attribute conveys a comma delimited list of platform
>> + specific cookies that identifies a QoS performance class
>> + for the persistent partition of the CXL mem device. These
>> + class-ids can be compared against a similar "qos_class"
>> + published for a root decoder. While it is not required
>> + that the endpoints map their local memory-class to a
>> + matching platform class, mismatches are not recommended
>> + and there are platform specific side-effects that may
>> + result.
>> +
>> +
>> What: /sys/bus/cxl/devices/memX/serial
>> Date: January, 2022
>> KernelVersion: v5.18
>> diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c
>> index 057a43267290..9366257e3183 100644
>> --- a/drivers/cxl/core/memdev.c
>> +++ b/drivers/cxl/core/memdev.c
>> @@ -77,6 +77,32 @@ static ssize_t ram_size_show(struct device *dev, struct device_attribute *attr,
>> static struct device_attribute dev_attr_ram_size =
>> __ATTR(size, 0444, ram_size_show, NULL);
>>
>> +static ssize_t ram_qos_class_show(struct device *dev,
>> + struct device_attribute *attr, char *buf)
>> +{
>> + struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
>> + struct cxl_dev_state *cxlds = cxlmd->cxlds;
>> + struct qos_class *qos_class = cxlds->ram_qos_class;
>> + int count, i;
>> +
>> + if (!qos_class)
>> + return 0;
>> +
>> + for (i = 0, count = 0; i < qos_class->nr; i++) {
>> + count += sysfs_emit_at(buf, count, "%d",
>> + qos_class->entries[i]);
>> + if (i + 1 == qos_class->nr)
>> + count += sysfs_emit_at(buf, count, "\n");
>> + else
>> + count += sysfs_emit_at(buf, count, ", ");
>> + }
>> +
>> + return count;
>> +}
>> +
>> +static struct device_attribute dev_attr_ram_qos_class =
>> + __ATTR(qos_class, 0444, ram_qos_class_show, NULL);
>> +
>> static ssize_t pmem_size_show(struct device *dev, struct device_attribute *attr,
>> char *buf)
>> {
>> @@ -90,6 +116,33 @@ static ssize_t pmem_size_show(struct device *dev, struct device_attribute *attr,
>> static struct device_attribute dev_attr_pmem_size =
>> __ATTR(size, 0444, pmem_size_show, NULL);
>>
>> +static ssize_t pmem_qos_class_show(struct device *dev,
>> + struct device_attribute *attr, char *buf)
>> +{
>> + struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
>> + struct cxl_dev_state *cxlds = cxlmd->cxlds;
>> + struct qos_class *qos_class = cxlds->pmem_qos_class;
>> + int count, i;
>> +
>> + if (!qos_class)
>> + return 0;
>> +
>> + for (i = 0, count = 0; i < qos_class->nr; i++) {
>> + count += sysfs_emit_at(buf, count, "%d",
>> + qos_class->entries[i]);
>> +
>> + if (i + 1 == qos_class->nr)
>> + count += sysfs_emit_at(buf, count, "\n");
>> + else
>> + count += sysfs_emit_at(buf, count, ", ");
>> + }
> Bunch of shred code here with the volatile case.
> Add a little utility function to avoid that?
ok
>> +
>> + return count;
>> +}
>> +
>> +static struct device_attribute dev_attr_pmem_qos_class =
>> + __ATTR(qos_class, 0444, pmem_qos_class_show, NULL);
>> +
>> static ssize_t serial_show(struct device *dev, struct device_attribute *attr,
>> char *buf)
>> {
>> @@ -344,11 +397,13 @@ static struct attribute *cxl_memdev_attributes[] = {
>>
>> static struct attribute *cxl_memdev_pmem_attributes[] = {
>> &dev_attr_pmem_size.attr,
>> + &dev_attr_pmem_qos_class.attr,
>> NULL,
>> };
>>
>> static struct attribute *cxl_memdev_ram_attributes[] = {
>> &dev_attr_ram_size.attr,
>> + &dev_attr_ram_qos_class.attr,
>> NULL,
>> };
>>
>>
>>
next prev parent reply other threads:[~2023-06-01 17:14 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-19 17:06 [PATCH v6 00/11] cxl: Add support for QTG ID retrieval for CXL subsystem Dave Jiang
2023-05-19 17:06 ` [PATCH v6 01/11] cxl: Add callback to parse the DSMAS subtables from CDAT Dave Jiang
2023-05-25 16:43 ` Jonathan Cameron
2023-05-19 17:06 ` [PATCH v6 02/11] cxl: Add callback to parse the DSLBIS subtable " Dave Jiang
2023-05-19 17:06 ` [PATCH v6 03/11] cxl: Add callback to parse the SSLBIS " Dave Jiang
2023-05-19 17:06 ` [PATCH v6 04/11] cxl: Add support for _DSM Function for retrieving QTG ID Dave Jiang
2023-05-25 16:44 ` Jonathan Cameron
2023-05-25 21:09 ` Dave Jiang
2023-05-19 17:07 ` [PATCH v6 05/11] cxl: Calculate and store PCI link latency for the downstream ports Dave Jiang
2023-05-19 17:07 ` [PATCH v6 06/11] cxl: Store the access coordinates for the generic ports Dave Jiang
2023-06-01 14:20 ` Jonathan Cameron
2023-05-19 17:07 ` [PATCH v6 07/11] cxl: Add helper function that calculate performance data for downstream ports Dave Jiang
2023-05-19 17:07 ` [PATCH v6 08/11] cxl: Compute the entire CXL path latency and bandwidth data Dave Jiang
2023-05-19 17:07 ` [PATCH v6 09/11] cxl: Store QTG IDs and related info to the CXL memory device context Dave Jiang
2023-06-01 14:32 ` Jonathan Cameron
2023-05-19 17:07 ` [PATCH v6 10/11] cxl: Export sysfs attributes for memory device QoS class Dave Jiang
2023-06-01 14:30 ` Jonathan Cameron
2023-06-01 17:13 ` Dave Jiang [this message]
2023-05-19 17:07 ` [PATCH v6 11/11] cxl/mem: Add debugfs output for QTG related data Dave Jiang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=8081b4a3-8c86-5b6b-e972-a09eb98367c2@intel.com \
--to=dave.jiang@intel.com \
--cc=Jonathan.Cameron@Huawei.com \
--cc=alison.schofield@intel.com \
--cc=dan.j.williams@intel.com \
--cc=ira.weiny@intel.com \
--cc=linux-cxl@vger.kernel.org \
--cc=vishal.l.verma@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox