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From: Terry Bowman <terry.bowman@amd.com>
To: <alison.schofield@intel.com>, <vishal.l.verma@intel.com>,
	<ira.weiny@intel.com>, <bwidawsk@kernel.org>,
	<dan.j.williams@intel.com>, <dave.jiang@intel.com>,
	<Jonathan.Cameron@huawei.com>, <linux-cxl@vger.kernel.org>
Cc: <terry.bowman@amd.com>, <rrichter@amd.com>,
	<linux-kernel@vger.kernel.org>, <bhelgaas@google.com>
Subject: [PATCH v9 01/15] cxl/port: Pre-initialize component register mappings
Date: Fri, 25 Aug 2023 18:31:57 -0500	[thread overview]
Message-ID: <20230825233211.3029825-2-terry.bowman@amd.com> (raw)
In-Reply-To: <20230825233211.3029825-1-terry.bowman@amd.com>

From: Robert Richter <rrichter@amd.com>

The component registers of a component may not exist or are not
needed. The setup may fail for that reason. In some cases the
initialization should continue anyway. Thus, always initialize struct
cxl_register_map with valid values. In case of errors, zero it, set a
value for @dev and make @resource a the valid value using
CXL_RESOURCE_NONE.

Signed-off-by: Robert Richter <rrichter@amd.com>
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
---
 drivers/cxl/core/port.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 724be8448eb4..2d22e7a5629b 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -693,16 +693,17 @@ static struct cxl_port *cxl_port_alloc(struct device *uport_dev,
 static int cxl_setup_comp_regs(struct device *dev, struct cxl_register_map *map,
 			       resource_size_t component_reg_phys)
 {
-	if (component_reg_phys == CXL_RESOURCE_NONE)
-		return 0;
-
 	*map = (struct cxl_register_map) {
 		.dev = dev,
-		.reg_type = CXL_REGLOC_RBI_COMPONENT,
 		.resource = component_reg_phys,
-		.max_size = CXL_COMPONENT_REG_BLOCK_SIZE,
 	};
 
+	if (component_reg_phys == CXL_RESOURCE_NONE)
+		return 0;
+
+	map->reg_type = CXL_REGLOC_RBI_COMPONENT;
+	map->max_size = CXL_COMPONENT_REG_BLOCK_SIZE;
+
 	return cxl_setup_regs(map);
 }
 
-- 
2.34.1


  reply	other threads:[~2023-08-25 23:33 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-25 23:31 [PATCH v9 00/15] cxl/pci: Add support for RCH RAS error handling Terry Bowman
2023-08-25 23:31 ` Terry Bowman [this message]
2023-08-29 13:38   ` [PATCH v9 01/15] cxl/port: Pre-initialize component register mappings Jonathan Cameron
2023-08-31 12:22     ` Robert Richter
2023-09-01  9:06       ` Jonathan Cameron
2023-08-25 23:31 ` [PATCH v9 02/15] cxl/regs: Prepare for multiple users of " Terry Bowman
2023-08-29 13:52   ` Jonathan Cameron
2023-08-31 12:43     ` Robert Richter
2023-09-01  9:08       ` Jonathan Cameron
2023-08-31 18:11   ` Dan Williams
2023-09-01  9:10     ` Jonathan Cameron
2023-08-25 23:31 ` [PATCH v9 03/15] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state Terry Bowman
2023-08-25 23:32 ` [PATCH v9 04/15] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability Terry Bowman
2023-08-25 23:32 ` [PATCH v9 05/15] cxl/pci: Remove Component Register base address from struct cxl_dev_state Terry Bowman
2023-08-25 23:32 ` [PATCH v9 06/15] cxl/port: Remove Component Register base address from struct cxl_port Terry Bowman
2023-08-25 23:32 ` [PATCH v9 07/15] cxl/pci: Add RCH downstream port AER register discovery Terry Bowman
2023-08-25 23:32 ` [PATCH v9 08/15] PCI/AER: Refactor cper_print_aer() for use by CXL driver module Terry Bowman
2023-08-25 23:32 ` [PATCH v9 09/15] cxl/pci: Update CXL error logging to use RAS register address Terry Bowman
2023-08-25 23:32 ` [PATCH v9 10/15] cxl/pci: Map RCH downstream AER registers for logging protocol errors Terry Bowman
2023-08-25 23:32 ` [PATCH v9 11/15] cxl/pci: Add RCH downstream port error logging Terry Bowman
2023-08-25 23:32 ` [PATCH v9 12/15] cxl/pci: Disable root port interrupts in RCH mode Terry Bowman
2023-08-25 23:32 ` [PATCH v9 13/15] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler Terry Bowman
2023-08-25 23:32 ` [PATCH v9 14/15] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling Terry Bowman
2023-08-25 23:32 ` [PATCH v9 15/15] cxl/core/regs: Rename phys_addr in cxl_map_component_regs() Terry Bowman
2023-08-29 13:54   ` Jonathan Cameron

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