From: Robert Richter <rrichter@amd.com>
To: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Terry Bowman <terry.bowman@amd.com>,
alison.schofield@intel.com, vishal.l.verma@intel.com,
ira.weiny@intel.com, bwidawsk@kernel.org,
dan.j.williams@intel.com, dave.jiang@intel.com,
linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org,
bhelgaas@google.com
Subject: Re: [PATCH v9 02/15] cxl/regs: Prepare for multiple users of register mappings
Date: Thu, 31 Aug 2023 14:43:53 +0200 [thread overview]
Message-ID: <ZPCLCSngB95EGBMk@rric.localdomain> (raw)
In-Reply-To: <20230829145254.00003259@Huawei.com>
On 29.08.23 14:52:54, Jonathan Cameron wrote:
> On Fri, 25 Aug 2023 18:31:58 -0500
> Terry Bowman <terry.bowman@amd.com> wrote:
>
> > From: Robert Richter <rrichter@amd.com>
> >
> > The function devm_cxl_iomap_block() is used to map register mappings
> > of CXL component or device registers. A @dev is used to unmap the IO
> > regions during device removal.
> >
> > Now, there are multiple devices using the register mappings. E.g. the
> > RAS cap of the Component Registers is used by cxl_pci, the HDM cap
> > used in cxl_mem. This could cause IO blocks not being freed and a
> > subsequent reinitialization to fail if the same device is used for
> > both.
> >
> > To prevent that, expand cxl_map_component_regs() to pass a @dev to be
> > used with devm to IO unmap. This allows to pass the device that
> > actually is creating and using the IO region.
> >
> > For symmetry also change the function i/f of cxl_map_device_regs().
> >
> > Signed-off-by: Robert Richter <rrichter@amd.com>
> > Signed-off-by: Terry Bowman <terry.bowman@amd.com>
>
> I'm not sure we should leave map->dev around after this change
> as it's not obvious where it is valid to use and where it isn't.
>
> Perhaps we just need to pass the device into the few calls
> that use it other than the ones you have here.
I have checked that and it turned out we would need to pass @dev
through multiple functions (see cxl_setup_regs()). So I left it in as
devm is a special case (mis)using it.
>
> This patch itself looks fine to me.
I will take it as a Reviewed-by:?
Thanks,
-Robert
>
> Jonathan
>
> > ---
> > drivers/cxl/core/hdm.c | 3 ++-
> > drivers/cxl/core/regs.c | 4 ++--
> > drivers/cxl/cxl.h | 2 ++
> > drivers/cxl/pci.c | 4 ++--
> > 4 files changed, 8 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
> > index 4449b34a80cc..17c8ba8c75e0 100644
> > --- a/drivers/cxl/core/hdm.c
> > +++ b/drivers/cxl/core/hdm.c
> > @@ -98,7 +98,8 @@ static int map_hdm_decoder_regs(struct cxl_port *port, void __iomem *crb,
> > return -ENODEV;
> > }
> >
> > - return cxl_map_component_regs(&map, regs, BIT(CXL_CM_CAP_CAP_ID_HDM));
> > + return cxl_map_component_regs(&map, &port->dev, regs,
> > + BIT(CXL_CM_CAP_CAP_ID_HDM));
> > }
> >
> > static bool should_emulate_decoders(struct cxl_endpoint_dvsec_info *info)
> > diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
> > index 6281127b3e9d..dfc3e272e7d8 100644
> > --- a/drivers/cxl/core/regs.c
> > +++ b/drivers/cxl/core/regs.c
> > @@ -201,10 +201,10 @@ void __iomem *devm_cxl_iomap_block(struct device *dev, resource_size_t addr,
> > }
> >
> > int cxl_map_component_regs(const struct cxl_register_map *map,
> > + struct device *dev,
> > struct cxl_component_regs *regs,
> > unsigned long map_mask)
> > {
> > - struct device *dev = map->dev;
> > struct mapinfo {
> > const struct cxl_reg_map *rmap;
> > void __iomem **addr;
> > @@ -235,9 +235,9 @@ int cxl_map_component_regs(const struct cxl_register_map *map,
> > EXPORT_SYMBOL_NS_GPL(cxl_map_component_regs, CXL);
> >
> > int cxl_map_device_regs(const struct cxl_register_map *map,
> > + struct device *dev,
> > struct cxl_device_regs *regs)
> > {
> > - struct device *dev = map->dev;
> > resource_size_t phys_addr = map->resource;
> > struct mapinfo {
> > const struct cxl_reg_map *rmap;
> > diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> > index 76d92561af29..ec8ba9ebcf64 100644
> > --- a/drivers/cxl/cxl.h
> > +++ b/drivers/cxl/cxl.h
> > @@ -274,9 +274,11 @@ void cxl_probe_component_regs(struct device *dev, void __iomem *base,
> > void cxl_probe_device_regs(struct device *dev, void __iomem *base,
> > struct cxl_device_reg_map *map);
> > int cxl_map_component_regs(const struct cxl_register_map *map,
> > + struct device *dev,
> > struct cxl_component_regs *regs,
> > unsigned long map_mask);
> > int cxl_map_device_regs(const struct cxl_register_map *map,
> > + struct device *dev,
> > struct cxl_device_regs *regs);
> > int cxl_map_pmu_regs(struct pci_dev *pdev, struct cxl_pmu_regs *regs,
> > struct cxl_register_map *map);
> > diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> > index 48f88d96029d..88ddcff8a0b2 100644
> > --- a/drivers/cxl/pci.c
> > +++ b/drivers/cxl/pci.c
> > @@ -827,7 +827,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
> > if (rc)
> > return rc;
> >
> > - rc = cxl_map_device_regs(&map, &cxlds->regs.device_regs);
> > + rc = cxl_map_device_regs(&map, cxlds->dev, &cxlds->regs.device_regs);
> > if (rc)
> > return rc;
> >
> > @@ -844,7 +844,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
> >
> > cxlds->component_reg_phys = map.resource;
> >
> > - rc = cxl_map_component_regs(&map, &cxlds->regs.component,
> > + rc = cxl_map_component_regs(&map, cxlds->dev, &cxlds->regs.component,
> > BIT(CXL_CM_CAP_CAP_ID_RAS));
> > if (rc)
> > dev_dbg(&pdev->dev, "Failed to map RAS capability.\n");
>
next prev parent reply other threads:[~2023-08-31 12:44 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-25 23:31 [PATCH v9 00/15] cxl/pci: Add support for RCH RAS error handling Terry Bowman
2023-08-25 23:31 ` [PATCH v9 01/15] cxl/port: Pre-initialize component register mappings Terry Bowman
2023-08-29 13:38 ` Jonathan Cameron
2023-08-31 12:22 ` Robert Richter
2023-09-01 9:06 ` Jonathan Cameron
2023-08-25 23:31 ` [PATCH v9 02/15] cxl/regs: Prepare for multiple users of " Terry Bowman
2023-08-29 13:52 ` Jonathan Cameron
2023-08-31 12:43 ` Robert Richter [this message]
2023-09-01 9:08 ` Jonathan Cameron
2023-08-31 18:11 ` Dan Williams
2023-09-01 9:10 ` Jonathan Cameron
2023-08-25 23:31 ` [PATCH v9 03/15] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state Terry Bowman
2023-08-25 23:32 ` [PATCH v9 04/15] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability Terry Bowman
2023-08-25 23:32 ` [PATCH v9 05/15] cxl/pci: Remove Component Register base address from struct cxl_dev_state Terry Bowman
2023-08-25 23:32 ` [PATCH v9 06/15] cxl/port: Remove Component Register base address from struct cxl_port Terry Bowman
2023-08-25 23:32 ` [PATCH v9 07/15] cxl/pci: Add RCH downstream port AER register discovery Terry Bowman
2023-08-25 23:32 ` [PATCH v9 08/15] PCI/AER: Refactor cper_print_aer() for use by CXL driver module Terry Bowman
2023-08-25 23:32 ` [PATCH v9 09/15] cxl/pci: Update CXL error logging to use RAS register address Terry Bowman
2023-08-25 23:32 ` [PATCH v9 10/15] cxl/pci: Map RCH downstream AER registers for logging protocol errors Terry Bowman
2023-08-25 23:32 ` [PATCH v9 11/15] cxl/pci: Add RCH downstream port error logging Terry Bowman
2023-08-25 23:32 ` [PATCH v9 12/15] cxl/pci: Disable root port interrupts in RCH mode Terry Bowman
2023-08-25 23:32 ` [PATCH v9 13/15] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler Terry Bowman
2023-08-25 23:32 ` [PATCH v9 14/15] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling Terry Bowman
2023-08-25 23:32 ` [PATCH v9 15/15] cxl/core/regs: Rename phys_addr in cxl_map_component_regs() Terry Bowman
2023-08-29 13:54 ` Jonathan Cameron
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