From: Terry Bowman <terry.bowman@amd.com>
To: <alison.schofield@intel.com>, <vishal.l.verma@intel.com>,
<ira.weiny@intel.com>, <bwidawsk@kernel.org>,
<dan.j.williams@intel.com>, <dave.jiang@intel.com>,
<Jonathan.Cameron@huawei.com>, <linux-cxl@vger.kernel.org>
Cc: <terry.bowman@amd.com>, <rrichter@amd.com>,
<linux-kernel@vger.kernel.org>, <bhelgaas@google.com>
Subject: [PATCH v10 15/15] cxl/core/regs: Rename phys_addr in cxl_map_component_regs()
Date: Thu, 31 Aug 2023 12:02:48 -0500 [thread overview]
Message-ID: <20230831170248.185078-8-terry.bowman@amd.com> (raw)
In-Reply-To: <20230831170248.185078-1-terry.bowman@amd.com>
From: Robert Richter <rrichter@amd.com>
Trivial change that renames variable phys_addr in
cxl_map_component_regs() to shorten its length to keep the 80 char
size limit for the line and also for consistency between the different
paths.
Signed-off-by: Robert Richter <rrichter@amd.com>
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
drivers/cxl/core/regs.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
index 5cb78b76c757..f8f26fe80489 100644
--- a/drivers/cxl/core/regs.c
+++ b/drivers/cxl/core/regs.c
@@ -217,16 +217,16 @@ int cxl_map_component_regs(const struct cxl_register_map *map,
for (i = 0; i < ARRAY_SIZE(mapinfo); i++) {
struct mapinfo *mi = &mapinfo[i];
- resource_size_t phys_addr;
+ resource_size_t addr;
resource_size_t length;
if (!mi->rmap->valid)
continue;
if (!test_bit(mi->rmap->id, &map_mask))
continue;
- phys_addr = map->resource + mi->rmap->offset;
+ addr = map->resource + mi->rmap->offset;
length = mi->rmap->size;
- *(mi->addr) = devm_cxl_iomap_block(dev, phys_addr, length);
+ *(mi->addr) = devm_cxl_iomap_block(dev, addr, length);
if (!*(mi->addr))
return -ENOMEM;
}
--
2.34.1
prev parent reply other threads:[~2023-08-31 17:04 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-31 17:02 [PATCH v10 08/15] PCI/AER: Refactor cper_print_aer() for use by CXL driver module Terry Bowman
2023-08-31 17:02 ` [PATCH v10 09/15] cxl/pci: Update CXL error logging to use RAS register address Terry Bowman
2023-08-31 17:02 ` [PATCH v10 10/15] cxl/pci: Map RCH downstream AER registers for logging protocol errors Terry Bowman
2023-09-15 0:27 ` Dan Williams
2023-08-31 17:02 ` [PATCH v10 11/15] cxl/pci: Add RCH downstream port error logging Terry Bowman
2023-08-31 17:02 ` [PATCH v10 12/15] cxl/pci: Disable root port interrupts in RCH mode Terry Bowman
2023-09-15 18:43 ` Dan Williams
2023-09-19 15:08 ` Terry Bowman
2023-09-26 21:47 ` Dan Williams
2023-08-31 17:02 ` [PATCH v10 13/15] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler Terry Bowman
2023-08-31 20:35 ` Dan Williams
2023-09-19 20:58 ` Terry Bowman
2023-09-20 15:28 ` Terry Bowman
2023-09-26 23:58 ` Dan Williams
2023-08-31 17:02 ` [PATCH v10 14/15] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling Terry Bowman
2023-08-31 17:02 ` Terry Bowman [this message]
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