From: Dan Williams <dan.j.williams@intel.com>
To: Terry Bowman <terry.bowman@amd.com>, <alison.schofield@intel.com>,
<vishal.l.verma@intel.com>, <ira.weiny@intel.com>,
<bwidawsk@kernel.org>, <dan.j.williams@intel.com>,
<dave.jiang@intel.com>, <Jonathan.Cameron@huawei.com>,
<linux-cxl@vger.kernel.org>
Cc: <terry.bowman@amd.com>, <rrichter@amd.com>,
<linux-kernel@vger.kernel.org>, <bhelgaas@google.com>
Subject: RE: [PATCH v10 12/15] cxl/pci: Disable root port interrupts in RCH mode
Date: Fri, 15 Sep 2023 11:43:46 -0700 [thread overview]
Message-ID: <6504a5e23cee9_d7cc8294b7@dwillia2-xfh.jf.intel.com.notmuch> (raw)
In-Reply-To: <20230831170248.185078-5-terry.bowman@amd.com>
Terry Bowman wrote:
> The RCH root port contains root command AER registers that should not be
> enabled.[1] Disable these to prevent root port interrupts.
>
> [1] CXL 3.0 - 12.2.1.1 RCH Downstream Port-detected Errors
>
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> Signed-off-by: Robert Richter <rrichter@amd.com>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
[..]
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index 2a22a7ed4704..d195af72ed65 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -1042,6 +1042,9 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev,
>
> cxl_dport_map_regs(dport);
>
> + if (dport->rch)
> + cxl_disable_rch_root_ints(dport);
> +
Similar to the comment about cxl_dport_map_regs() not being appropriate
in an enumeration routine, this also needs to move out of _add_dport. It
occurs to me that it should also be undone on driver detach just like
other device "enables".
next prev parent reply other threads:[~2023-09-15 18:57 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-31 17:02 [PATCH v10 08/15] PCI/AER: Refactor cper_print_aer() for use by CXL driver module Terry Bowman
2023-08-31 17:02 ` [PATCH v10 09/15] cxl/pci: Update CXL error logging to use RAS register address Terry Bowman
2023-08-31 17:02 ` [PATCH v10 10/15] cxl/pci: Map RCH downstream AER registers for logging protocol errors Terry Bowman
2023-09-15 0:27 ` Dan Williams
2023-08-31 17:02 ` [PATCH v10 11/15] cxl/pci: Add RCH downstream port error logging Terry Bowman
2023-08-31 17:02 ` [PATCH v10 12/15] cxl/pci: Disable root port interrupts in RCH mode Terry Bowman
2023-09-15 18:43 ` Dan Williams [this message]
2023-09-19 15:08 ` Terry Bowman
2023-09-26 21:47 ` Dan Williams
2023-08-31 17:02 ` [PATCH v10 13/15] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler Terry Bowman
2023-08-31 20:35 ` Dan Williams
2023-09-19 20:58 ` Terry Bowman
2023-09-20 15:28 ` Terry Bowman
2023-09-26 23:58 ` Dan Williams
2023-08-31 17:02 ` [PATCH v10 14/15] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling Terry Bowman
2023-08-31 17:02 ` [PATCH v10 15/15] cxl/core/regs: Rename phys_addr in cxl_map_component_regs() Terry Bowman
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