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From: nifan.cxl@gmail.com
To: qemu-devel@nongnu.org
Cc: jonathan.cameron@huawei.com, linux-cxl@vger.kernel.org,
	gregory.price@memverge.com, ira.weiny@intel.com,
	dan.j.williams@intel.com, a.manzanares@samsung.com,
	dave@stgolabs.net, nmtadam.samsung@gmail.com,
	nifan.cxl@gmail.com, jim.harris@samsung.com,
	Fan Ni <fan.ni@samsung.com>
Subject: [PATCH v4 05/10] hw/mem/cxl-type3: Refactor ct3_build_cdat_entries_for_mr to take mr size insead of mr as argument
Date: Wed, 21 Feb 2024 10:15:58 -0800	[thread overview]
Message-ID: <20240221182020.1086096-6-nifan.cxl@gmail.com> (raw)
In-Reply-To: <20240221182020.1086096-1-nifan.cxl@gmail.com>

From: Fan Ni <fan.ni@samsung.com>

The function ct3_build_cdat_entries_for_mr only uses size of the passed
memory region argument, refactor the function definition to make the passed
arguments more specific.

Signed-off-by: Fan Ni <fan.ni@samsung.com>
---
 hw/mem/cxl_type3.c | 15 +++++++++------
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index c61cd2b5ac..6e5f908fb1 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -43,7 +43,7 @@ enum {
 };
 
 static void ct3_build_cdat_entries_for_mr(CDATSubHeader **cdat_table,
-                                          int dsmad_handle, MemoryRegion *mr,
+                                          int dsmad_handle, uint64_t size,
                                           bool is_pmem, uint64_t dpa_base)
 {
     g_autofree CDATDsmas *dsmas = NULL;
@@ -62,7 +62,7 @@ static void ct3_build_cdat_entries_for_mr(CDATSubHeader **cdat_table,
         .DSMADhandle = dsmad_handle,
         .flags = is_pmem ? CDAT_DSMAS_FLAG_NV : 0,
         .DPA_base = dpa_base,
-        .DPA_length = memory_region_size(mr),
+        .DPA_length = size,
     };
 
     /* For now, no memory side cache, plausiblish numbers */
@@ -131,7 +131,7 @@ static void ct3_build_cdat_entries_for_mr(CDATSubHeader **cdat_table,
          */
         .EFI_memory_type_attr = is_pmem ? 2 : 1,
         .DPA_offset = 0,
-        .DPA_length = memory_region_size(mr),
+        .DPA_length = size,
     };
 
     /* Header always at start of structure */
@@ -148,6 +148,7 @@ static int ct3_build_cdat_table(CDATSubHeader ***cdat_table, void *priv)
     g_autofree CDATSubHeader **table = NULL;
     CXLType3Dev *ct3d = priv;
     MemoryRegion *volatile_mr = NULL, *nonvolatile_mr = NULL;
+    uint64_t vmr_size = 0, pmr_size = 0;
     int dsmad_handle = 0;
     int cur_ent = 0;
     int len = 0;
@@ -162,6 +163,7 @@ static int ct3_build_cdat_table(CDATSubHeader ***cdat_table, void *priv)
             return -EINVAL;
         }
         len += CT3_CDAT_NUM_ENTRIES;
+        vmr_size = memory_region_size(volatile_mr);
     }
 
     if (ct3d->hostpmem) {
@@ -170,21 +172,22 @@ static int ct3_build_cdat_table(CDATSubHeader ***cdat_table, void *priv)
             return -EINVAL;
         }
         len += CT3_CDAT_NUM_ENTRIES;
+        pmr_size = memory_region_size(nonvolatile_mr);
     }
 
     table = g_malloc0(len * sizeof(*table));
 
     /* Now fill them in */
     if (volatile_mr) {
-        ct3_build_cdat_entries_for_mr(table, dsmad_handle++, volatile_mr,
+        ct3_build_cdat_entries_for_mr(table, dsmad_handle++, vmr_size,
                                       false, 0);
         cur_ent = CT3_CDAT_NUM_ENTRIES;
     }
 
     if (nonvolatile_mr) {
-        uint64_t base = volatile_mr ? memory_region_size(volatile_mr) : 0;
+        uint64_t base = vmr_size;
         ct3_build_cdat_entries_for_mr(&(table[cur_ent]), dsmad_handle++,
-                                      nonvolatile_mr, true, base);
+                                      pmr_size, true, base);
         cur_ent += CT3_CDAT_NUM_ENTRIES;
     }
     assert(len == cur_ent);
-- 
2.43.0


  parent reply	other threads:[~2024-02-21 18:21 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-21 18:15 [PATCH v4 00/10] Enabling DCD emulation support in Qemu nifan.cxl
2024-02-21 18:15 ` [PATCH v4 01/10] hw/cxl/cxl-mailbox-utils: Add dc_event_log_size field to output payload of identify memory device command nifan.cxl
2024-02-21 18:15 ` [PATCH v4 02/10] hw/cxl/cxl-mailbox-utils: Add dynamic capacity region representative and mailbox command support nifan.cxl
2024-02-22  7:45   ` Wonjae Lee
2024-02-22 16:54     ` fan
2024-02-26 17:33   ` Jonathan Cameron
2024-02-26 19:16     ` fan
2024-03-04 12:40   ` Jørgen Hansen
2024-03-04 17:35     ` fan
2024-02-21 18:15 ` [PATCH v4 03/10] include/hw/cxl/cxl_device: Rename mem_size as static_mem_size for type3 memory devices nifan.cxl
2024-02-21 18:15 ` [PATCH v4 04/10] hw/mem/cxl_type3: Add support to create DC regions to " nifan.cxl
2024-02-26 17:38   ` Jonathan Cameron
2024-03-04 13:10   ` Jørgen Hansen
2024-03-04 17:31     ` fan
2024-02-21 18:15 ` nifan.cxl [this message]
2024-02-21 18:15 ` [PATCH v4 06/10] hw/mem/cxl_type3: Add host backend and address space handling for DC regions nifan.cxl
2024-02-22  9:22   ` Wonjae Lee
2024-02-22 16:56     ` fan
2024-02-26 17:45   ` Jonathan Cameron
2024-02-21 18:16 ` [PATCH v4 07/10] hw/mem/cxl_type3: Add DC extent list representative and get DC extent list mailbox support nifan.cxl
2024-02-23  7:16   ` Wonjae Lee
2024-02-23 16:56     ` fan
2024-02-26 17:48   ` Jonathan Cameron
2024-02-21 18:16 ` [PATCH v4 08/10] hw/cxl/cxl-mailbox-utils: Add mailbox commands to support add/release dynamic capacity response nifan.cxl
2024-02-23  9:10   ` Wonjae Lee
2024-02-26 18:04   ` Jonathan Cameron
2024-02-27  1:01     ` fan
2024-02-27 10:39       ` Jonathan Cameron
2024-03-01  3:56         ` fan
2024-03-06 14:58           ` Jonathan Cameron
2024-02-27  1:06     ` fan
2024-02-21 18:16 ` [PATCH v4 09/10] hw/cxl/events: Add qmp interfaces to add/release dynamic capacity extents nifan.cxl
2024-02-23 12:16   ` Wonjae Lee
2024-02-26 18:10   ` Jonathan Cameron
2024-02-21 18:16 ` [PATCH v4 10/10] hw/mem/cxl_type3: Add dpa range validation for accesses to DC regions nifan.cxl
2024-02-23 18:05 ` [PATCH v4 00/10] Enabling DCD emulation support in Qemu fan

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