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From: "Jørgen Hansen" <Jorgen.Hansen@wdc.com>
To: "nifan.cxl@gmail.com" <nifan.cxl@gmail.com>,
	"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Cc: "jonathan.cameron@huawei.com" <jonathan.cameron@huawei.com>,
	"linux-cxl@vger.kernel.org" <linux-cxl@vger.kernel.org>,
	"gregory.price@memverge.com" <gregory.price@memverge.com>,
	"ira.weiny@intel.com" <ira.weiny@intel.com>,
	"dan.j.williams@intel.com" <dan.j.williams@intel.com>,
	"a.manzanares@samsung.com" <a.manzanares@samsung.com>,
	"dave@stgolabs.net" <dave@stgolabs.net>,
	"nmtadam.samsung@gmail.com" <nmtadam.samsung@gmail.com>,
	"jim.harris@samsung.com" <jim.harris@samsung.com>,
	Fan Ni <fan.ni@samsung.com>
Subject: Re: [PATCH v4 04/10] hw/mem/cxl_type3: Add support to create DC regions to type3 memory devices
Date: Mon, 4 Mar 2024 13:10:37 +0000	[thread overview]
Message-ID: <ebab98e4-aa07-4aa6-84ec-768f6432e2f4@wdc.com> (raw)
In-Reply-To: <20240221182020.1086096-5-nifan.cxl@gmail.com>

On 2/21/24 19:15, nifan.cxl@gmail.com wrote:
> CAUTION: This email originated from outside of Western Digital. Do not click on links or open attachments unless you recognize the sender and know that the content is safe.
> 
> 
> From: Fan Ni <fan.ni@samsung.com>
> 
> With the change, when setting up memory for type3 memory device, we can
> create DC regions.
> A property 'num-dc-regions' is added to ct3_props to allow users to pass the
> number of DC regions to create. To make it easier, other region parameters
> like region base, length, and block size are hard coded. If needed,
> these parameters can be added easily.
> 
> With the change, we can create DC regions with proper kernel side
> support like below:
> 
> region=$(cat /sys/bus/cxl/devices/decoder0.0/create_dc_region)
> echo $region > /sys/bus/cxl/devices/decoder0.0/create_dc_region
> echo 256 > /sys/bus/cxl/devices/$region/interleave_granularity
> echo 1 > /sys/bus/cxl/devices/$region/interleave_ways
> 
> echo "dc0" >/sys/bus/cxl/devices/decoder2.0/mode
> echo 0x40000000 >/sys/bus/cxl/devices/decoder2.0/dpa_size
> 
> echo 0x40000000 > /sys/bus/cxl/devices/$region/size
> echo  "decoder2.0" > /sys/bus/cxl/devices/$region/target0
> echo 1 > /sys/bus/cxl/devices/$region/commit
> echo $region > /sys/bus/cxl/drivers/cxl_region/bind
> 
> However, we cannot really read/write to the DC regions due to lack of
> 1. host backend and address space setup for DC regions;
> 2. mailbox command support for adding/releasing DC extents.
> 
> Signed-off-by: Fan Ni <fan.ni@samsung.com>
> ---
>   hw/mem/cxl_type3.c | 40 ++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 40 insertions(+)
> 
> diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
> index 244d2b5fd5..c61cd2b5ac 100644
> --- a/hw/mem/cxl_type3.c
> +++ b/hw/mem/cxl_type3.c
> @@ -567,6 +567,40 @@ static void ct3d_reg_write(void *opaque, hwaddr offset, uint64_t value,
>       }
>   }
> 
> +/*
> + * TODO: dc region configuration will be updated once host backend and address
> + * space support is added for DCD.
> + */
> +static bool cxl_create_dc_regions(CXLType3Dev *ct3d, Error **errp)
> +{
> +    int i;
> +    uint64_t region_base = 0;
> +    uint64_t region_len =  2 * GiB;
> +    uint64_t decode_len = 2 * GiB;
> +    uint64_t blk_size = 2 * MiB;
> +    CXLDCDRegion *region;
> +
> +    if (ct3d->hostvmem) {
> +        region_base += ct3d->hostvmem->size;
> +    }
> +    if (ct3d->hostpmem) {
> +        region_base += ct3d->hostpmem->size;
> +    }

You could use memory_region_size() here instead of accessing field directly.

Also, it doesn't look like there is any enforcement of hostvmem and 
hostpmem being a multiple of 256MB, so region_base isn't necessarily 
aligned to 256MB either. This probably should be fixed separately for 
vmem and pmem, such that they check the size similar to what you do, as 
the existing code also assumes that they are multiples of 256MB.

> +    for (i = 0; i < ct3d->dc.num_regions; i++) {
> +        region = &ct3d->dc.regions[i];
> +        region->base = region_base;
> +        region->decode_len = decode_len;
> +        region->len = region_len;
> +        region->block_size = blk_size;
> +        /* dsmad_handle is set when creating cdat table entries */
> +        region->flags = 0;
> +
> +        region_base += region->len;
> +    }
> +
> +    return true;
> +}
> +
>   static bool cxl_setup_memory(CXLType3Dev *ct3d, Error **errp)
>   {
>       DeviceState *ds = DEVICE(ct3d);
> @@ -635,6 +669,11 @@ static bool cxl_setup_memory(CXLType3Dev *ct3d, Error **errp)
>           g_free(p_name);
>       }
> 
> +    if (!cxl_create_dc_regions(ct3d, errp)) {
> +        error_setg(errp, "setup DC regions failed");
> +        return false;
> +    }
> +
>       return true;
>   }
> 
> @@ -930,6 +969,7 @@ static Property ct3_props[] = {
>                        HostMemoryBackend *),
>       DEFINE_PROP_UINT64("sn", CXLType3Dev, sn, UI64_NULL),
>       DEFINE_PROP_STRING("cdat", CXLType3Dev, cxl_cstate.cdat.filename),
> +    DEFINE_PROP_UINT8("num-dc-regions", CXLType3Dev, dc.num_regions, 0),
>       DEFINE_PROP_END_OF_LIST(),
>   };
> 
> --
> 2.43.0
> 
> 

Thanks,
Jorgen

  parent reply	other threads:[~2024-03-04 13:10 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-21 18:15 [PATCH v4 00/10] Enabling DCD emulation support in Qemu nifan.cxl
2024-02-21 18:15 ` [PATCH v4 01/10] hw/cxl/cxl-mailbox-utils: Add dc_event_log_size field to output payload of identify memory device command nifan.cxl
2024-02-21 18:15 ` [PATCH v4 02/10] hw/cxl/cxl-mailbox-utils: Add dynamic capacity region representative and mailbox command support nifan.cxl
2024-02-22  7:45   ` Wonjae Lee
2024-02-22 16:54     ` fan
2024-02-26 17:33   ` Jonathan Cameron
2024-02-26 19:16     ` fan
2024-03-04 12:40   ` Jørgen Hansen
2024-03-04 17:35     ` fan
2024-02-21 18:15 ` [PATCH v4 03/10] include/hw/cxl/cxl_device: Rename mem_size as static_mem_size for type3 memory devices nifan.cxl
2024-02-21 18:15 ` [PATCH v4 04/10] hw/mem/cxl_type3: Add support to create DC regions to " nifan.cxl
2024-02-26 17:38   ` Jonathan Cameron
2024-03-04 13:10   ` Jørgen Hansen [this message]
2024-03-04 17:31     ` fan
2024-02-21 18:15 ` [PATCH v4 05/10] hw/mem/cxl-type3: Refactor ct3_build_cdat_entries_for_mr to take mr size insead of mr as argument nifan.cxl
2024-02-21 18:15 ` [PATCH v4 06/10] hw/mem/cxl_type3: Add host backend and address space handling for DC regions nifan.cxl
2024-02-22  9:22   ` Wonjae Lee
2024-02-22 16:56     ` fan
2024-02-26 17:45   ` Jonathan Cameron
2024-02-21 18:16 ` [PATCH v4 07/10] hw/mem/cxl_type3: Add DC extent list representative and get DC extent list mailbox support nifan.cxl
2024-02-23  7:16   ` Wonjae Lee
2024-02-23 16:56     ` fan
2024-02-26 17:48   ` Jonathan Cameron
2024-02-21 18:16 ` [PATCH v4 08/10] hw/cxl/cxl-mailbox-utils: Add mailbox commands to support add/release dynamic capacity response nifan.cxl
2024-02-23  9:10   ` Wonjae Lee
2024-02-26 18:04   ` Jonathan Cameron
2024-02-27  1:01     ` fan
2024-02-27 10:39       ` Jonathan Cameron
2024-03-01  3:56         ` fan
2024-03-06 14:58           ` Jonathan Cameron
2024-02-27  1:06     ` fan
2024-02-21 18:16 ` [PATCH v4 09/10] hw/cxl/events: Add qmp interfaces to add/release dynamic capacity extents nifan.cxl
2024-02-23 12:16   ` Wonjae Lee
2024-02-26 18:10   ` Jonathan Cameron
2024-02-21 18:16 ` [PATCH v4 10/10] hw/mem/cxl_type3: Add dpa range validation for accesses to DC regions nifan.cxl
2024-02-23 18:05 ` [PATCH v4 00/10] Enabling DCD emulation support in Qemu fan

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