* [PATCH v3 1/3] cxl: Remove checking of iter in cxl_endpoint_get_perf_coordinates() @ 2024-03-06 17:52 Dave Jiang 2024-03-06 17:52 ` [PATCH v3 2/3] cxl: Consolidate dport access_coordinate ->hb_coord and ->sw_coord into ->coord Dave Jiang 2024-03-06 17:52 ` [PATCH v3 3/3] cxl: Add checks to access_coordinate calculation to fail missing data Dave Jiang 0 siblings, 2 replies; 5+ messages in thread From: Dave Jiang @ 2024-03-06 17:52 UTC (permalink / raw) To: linux-cxl Cc: dan.j.williams, ira.weiny, vishal.l.verma, alison.schofield, Jonathan.Cameron, dave The while() loop in cxl_endpoint_get_perf_coordinates() checks to see if 'iter' is valid as part of the condition breaking out of the loop. However, iter is being used before the check at the end of the while loop before the next iteration starts. Given that the loop doesn't expect the iter to be NULL because it stops before the root port, remove the iter check. The presence of the iter or removing the iter does not impact the behavior of the code. This is a code clean up and not a bug fix. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> --- drivers/cxl/core/port.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index e59d9d37aa65..e1d30a885700 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -2142,7 +2142,7 @@ int cxl_endpoint_get_perf_coordinates(struct cxl_port *port, * port each iteration. If the parent is cxl root then there is * nothing to gather. */ - while (iter && !is_cxl_root(to_cxl_port(iter->dev.parent))) { + while (!is_cxl_root(to_cxl_port(iter->dev.parent))) { combine_coordinates(&c, &dport->sw_coord); c.write_latency += dport->link_latency; c.read_latency += dport->link_latency; -- 2.43.0 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v3 2/3] cxl: Consolidate dport access_coordinate ->hb_coord and ->sw_coord into ->coord 2024-03-06 17:52 [PATCH v3 1/3] cxl: Remove checking of iter in cxl_endpoint_get_perf_coordinates() Dave Jiang @ 2024-03-06 17:52 ` Dave Jiang 2024-03-07 12:53 ` Jonathan Cameron 2024-03-06 17:52 ` [PATCH v3 3/3] cxl: Add checks to access_coordinate calculation to fail missing data Dave Jiang 1 sibling, 1 reply; 5+ messages in thread From: Dave Jiang @ 2024-03-06 17:52 UTC (permalink / raw) To: linux-cxl Cc: dan.j.williams, ira.weiny, vishal.l.verma, alison.schofield, Jonathan.Cameron, dave The driver stores access_coordinate for host bridge in ->hb_coord and switch CDAT access_coordinate in ->sw_coord. Since neither of these access_coordinate clobber each other, the variable name can be consolidated into ->coord to simplify the code. This change also simplifies the iteration loop in cxl_endpoint_get_perf_coordinates() and allow all the access_coordinate to be picked up in the loop. Signed-off-by: Dave Jiang <dave.jiang@intel.com> --- drivers/cxl/acpi.c | 6 +++--- drivers/cxl/core/cdat.c | 2 +- drivers/cxl/core/port.c | 5 +---- drivers/cxl/cxl.h | 6 ++---- 4 files changed, 7 insertions(+), 12 deletions(-) diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c index 1a3e6aafbdcc..dbd5a0d10f8b 100644 --- a/drivers/cxl/acpi.c +++ b/drivers/cxl/acpi.c @@ -530,13 +530,13 @@ static int get_genport_coordinates(struct device *dev, struct cxl_dport *dport) if (kstrtou32(acpi_device_uid(hb), 0, &uid)) return -EINVAL; - rc = acpi_get_genport_coordinates(uid, &dport->hb_coord); + rc = acpi_get_genport_coordinates(uid, &dport->coord); if (rc < 0) return rc; /* Adjust back to picoseconds from nanoseconds */ - dport->hb_coord.read_latency *= 1000; - dport->hb_coord.write_latency *= 1000; + dport->coord.read_latency *= 1000; + dport->coord.write_latency *= 1000; return 0; } diff --git a/drivers/cxl/core/cdat.c b/drivers/cxl/core/cdat.c index 0363ca434ef4..fcfb6308996b 100644 --- a/drivers/cxl/core/cdat.c +++ b/drivers/cxl/core/cdat.c @@ -460,7 +460,7 @@ static int cdat_sslbis_handler(union acpi_subtable_headers *header, void *arg, xa_for_each(&port->dports, index, dport) { if (dsp_id == ACPI_CDAT_SSLBIS_ANY_PORT || dsp_id == dport->port_id) - cxl_access_coordinate_set(&dport->sw_coord, + cxl_access_coordinate_set(&dport->coord, sslbis->data_type, val); } diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index e1d30a885700..6fa273677963 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -2143,7 +2143,7 @@ int cxl_endpoint_get_perf_coordinates(struct cxl_port *port, * nothing to gather. */ while (!is_cxl_root(to_cxl_port(iter->dev.parent))) { - combine_coordinates(&c, &dport->sw_coord); + combine_coordinates(&c, &dport->coord); c.write_latency += dport->link_latency; c.read_latency += dport->link_latency; @@ -2151,9 +2151,6 @@ int cxl_endpoint_get_perf_coordinates(struct cxl_port *port, dport = iter->parent_dport; } - /* Augment with the generic port (host bridge) perf data */ - combine_coordinates(&c, &dport->hb_coord); - /* Get the calculated PCI paths bandwidth */ pdev = to_pci_dev(port->uport_dev->parent); bw = pcie_bandwidth_available(pdev, NULL, NULL, NULL); diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 003feebab79b..0cf5f23d9de6 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -658,8 +658,7 @@ struct cxl_rcrb_info { * @rch: Indicate whether this dport was enumerated in RCH or VH mode * @port: reference to cxl_port that contains this downstream port * @regs: Dport parsed register blocks - * @sw_coord: access coordinates (performance) for switch from CDAT - * @hb_coord: access coordinates (performance) from ACPI generic port (host bridge) + * @coord: access coordinates (bandwidth and latency performance attributes) * @link_latency: calculated PCIe downstream latency */ struct cxl_dport { @@ -670,8 +669,7 @@ struct cxl_dport { bool rch; struct cxl_port *port; struct cxl_regs regs; - struct access_coordinate sw_coord; - struct access_coordinate hb_coord; + struct access_coordinate coord; long link_latency; }; -- 2.43.0 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v3 2/3] cxl: Consolidate dport access_coordinate ->hb_coord and ->sw_coord into ->coord 2024-03-06 17:52 ` [PATCH v3 2/3] cxl: Consolidate dport access_coordinate ->hb_coord and ->sw_coord into ->coord Dave Jiang @ 2024-03-07 12:53 ` Jonathan Cameron 0 siblings, 0 replies; 5+ messages in thread From: Jonathan Cameron @ 2024-03-07 12:53 UTC (permalink / raw) To: Dave Jiang Cc: linux-cxl, dan.j.williams, ira.weiny, vishal.l.verma, alison.schofield, dave On Wed, 6 Mar 2024 10:52:03 -0700 Dave Jiang <dave.jiang@intel.com> wrote: > The driver stores access_coordinate for host bridge in ->hb_coord and switch > CDAT access_coordinate in ->sw_coord. Since neither of these > access_coordinate clobber each other, the variable name can be consolidated > into ->coord to simplify the code. This change also simplifies the iteration > loop in cxl_endpoint_get_perf_coordinates() and allow all the > access_coordinate to be picked up in the loop. > > Signed-off-by: Dave Jiang <dave.jiang@intel.com> Makes sense - can only be one set of access characteristics for a dport, just coming from different sources depending on which dport it is. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > --- > drivers/cxl/acpi.c | 6 +++--- > drivers/cxl/core/cdat.c | 2 +- > drivers/cxl/core/port.c | 5 +---- > drivers/cxl/cxl.h | 6 ++---- > 4 files changed, 7 insertions(+), 12 deletions(-) > > diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c > index 1a3e6aafbdcc..dbd5a0d10f8b 100644 > --- a/drivers/cxl/acpi.c > +++ b/drivers/cxl/acpi.c > @@ -530,13 +530,13 @@ static int get_genport_coordinates(struct device *dev, struct cxl_dport *dport) > if (kstrtou32(acpi_device_uid(hb), 0, &uid)) > return -EINVAL; > > - rc = acpi_get_genport_coordinates(uid, &dport->hb_coord); > + rc = acpi_get_genport_coordinates(uid, &dport->coord); > if (rc < 0) > return rc; > > /* Adjust back to picoseconds from nanoseconds */ > - dport->hb_coord.read_latency *= 1000; > - dport->hb_coord.write_latency *= 1000; > + dport->coord.read_latency *= 1000; > + dport->coord.write_latency *= 1000; > > return 0; > } > diff --git a/drivers/cxl/core/cdat.c b/drivers/cxl/core/cdat.c > index 0363ca434ef4..fcfb6308996b 100644 > --- a/drivers/cxl/core/cdat.c > +++ b/drivers/cxl/core/cdat.c > @@ -460,7 +460,7 @@ static int cdat_sslbis_handler(union acpi_subtable_headers *header, void *arg, > xa_for_each(&port->dports, index, dport) { > if (dsp_id == ACPI_CDAT_SSLBIS_ANY_PORT || > dsp_id == dport->port_id) > - cxl_access_coordinate_set(&dport->sw_coord, > + cxl_access_coordinate_set(&dport->coord, > sslbis->data_type, > val); > } > diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c > index e1d30a885700..6fa273677963 100644 > --- a/drivers/cxl/core/port.c > +++ b/drivers/cxl/core/port.c > @@ -2143,7 +2143,7 @@ int cxl_endpoint_get_perf_coordinates(struct cxl_port *port, > * nothing to gather. > */ > while (!is_cxl_root(to_cxl_port(iter->dev.parent))) { > - combine_coordinates(&c, &dport->sw_coord); > + combine_coordinates(&c, &dport->coord); > c.write_latency += dport->link_latency; > c.read_latency += dport->link_latency; > > @@ -2151,9 +2151,6 @@ int cxl_endpoint_get_perf_coordinates(struct cxl_port *port, > dport = iter->parent_dport; > } > > - /* Augment with the generic port (host bridge) perf data */ > - combine_coordinates(&c, &dport->hb_coord); > - > /* Get the calculated PCI paths bandwidth */ > pdev = to_pci_dev(port->uport_dev->parent); > bw = pcie_bandwidth_available(pdev, NULL, NULL, NULL); > diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h > index 003feebab79b..0cf5f23d9de6 100644 > --- a/drivers/cxl/cxl.h > +++ b/drivers/cxl/cxl.h > @@ -658,8 +658,7 @@ struct cxl_rcrb_info { > * @rch: Indicate whether this dport was enumerated in RCH or VH mode > * @port: reference to cxl_port that contains this downstream port > * @regs: Dport parsed register blocks > - * @sw_coord: access coordinates (performance) for switch from CDAT > - * @hb_coord: access coordinates (performance) from ACPI generic port (host bridge) > + * @coord: access coordinates (bandwidth and latency performance attributes) > * @link_latency: calculated PCIe downstream latency > */ > struct cxl_dport { > @@ -670,8 +669,7 @@ struct cxl_dport { > bool rch; > struct cxl_port *port; > struct cxl_regs regs; > - struct access_coordinate sw_coord; > - struct access_coordinate hb_coord; > + struct access_coordinate coord; > long link_latency; > }; > ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v3 3/3] cxl: Add checks to access_coordinate calculation to fail missing data 2024-03-06 17:52 [PATCH v3 1/3] cxl: Remove checking of iter in cxl_endpoint_get_perf_coordinates() Dave Jiang 2024-03-06 17:52 ` [PATCH v3 2/3] cxl: Consolidate dport access_coordinate ->hb_coord and ->sw_coord into ->coord Dave Jiang @ 2024-03-06 17:52 ` Dave Jiang 2024-03-07 12:59 ` Jonathan Cameron 1 sibling, 1 reply; 5+ messages in thread From: Dave Jiang @ 2024-03-06 17:52 UTC (permalink / raw) To: linux-cxl Cc: dan.j.williams, ira.weiny, vishal.l.verma, alison.schofield, Jonathan.Cameron, dave Jonathan noted that when the coordinates for host bridge and switches can be 0s if no actual data are retrieved and the calculation continues. The resulting number would be inaccurate. Add checks to ensure that the calculation would complete only if the numbers are valid. While not seen in the wild, issue may show up with a BIOS that reported CXL root ports via Generic Ports (via a PCI handle in the SRAT entry). Fixes: 14a6960b3e92 ("cxl: Add helper function that calculate performance data for downstream ports") Reported-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> --- v3: - Simplify iteration loop in cxl_endpoint_get_perf_coordinates(). (Jonathan) --- drivers/cxl/core/port.c | 33 +++++++++++++++++++++++---------- 1 file changed, 23 insertions(+), 10 deletions(-) diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 6fa273677963..baaaeddae775 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -2110,6 +2110,20 @@ static void combine_coordinates(struct access_coordinate *c1, c1->read_latency += c2->read_latency; } +static bool coordinates_invalid(struct access_coordinate *c) +{ + if (!c->read_bandwidth && !c->write_bandwidth && + !c->read_latency && !c->write_latency) + return true; + + return false; +} + +static bool parent_port_is_cxl_root(struct cxl_port *port) +{ + return is_cxl_root(to_cxl_port(port->dev.parent)); +} + /** * cxl_endpoint_get_perf_coordinates - Retrieve performance numbers stored in dports * of CXL path @@ -2133,23 +2147,22 @@ int cxl_endpoint_get_perf_coordinates(struct cxl_port *port, if (!is_cxl_endpoint(port)) return -EINVAL; - dport = iter->parent_dport; - /* - * Exit the loop when the parent port of the current port is cxl root. - * The iterative loop starts at the endpoint and gathers the - * latency of the CXL link from the current iter to the next downstream - * port each iteration. If the parent is cxl root then there is - * nothing to gather. + * Exit the loop when the parent port of the current iter port is cxl + * root. The iterative loop starts at the endpoint and gathers the + * latency of the CXL link from the current device/port to the connected + * downstream port each iteration. */ - while (!is_cxl_root(to_cxl_port(iter->dev.parent))) { + do { + dport = iter->parent_dport; + if (coordinates_invalid(&dport->coord)) + return -EINVAL; combine_coordinates(&c, &dport->coord); c.write_latency += dport->link_latency; c.read_latency += dport->link_latency; iter = to_cxl_port(iter->dev.parent); - dport = iter->parent_dport; - } + } while (!parent_port_is_cxl_root(iter)); /* Get the calculated PCI paths bandwidth */ pdev = to_pci_dev(port->uport_dev->parent); -- 2.43.0 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v3 3/3] cxl: Add checks to access_coordinate calculation to fail missing data 2024-03-06 17:52 ` [PATCH v3 3/3] cxl: Add checks to access_coordinate calculation to fail missing data Dave Jiang @ 2024-03-07 12:59 ` Jonathan Cameron 0 siblings, 0 replies; 5+ messages in thread From: Jonathan Cameron @ 2024-03-07 12:59 UTC (permalink / raw) To: Dave Jiang Cc: linux-cxl, dan.j.williams, ira.weiny, vishal.l.verma, alison.schofield, dave On Wed, 6 Mar 2024 10:52:04 -0700 Dave Jiang <dave.jiang@intel.com> wrote: > Jonathan noted that when the coordinates for host bridge and switches > can be 0s if no actual data are retrieved and the calculation continues. > The resulting number would be inaccurate. Add checks to ensure that the > calculation would complete only if the numbers are valid. > > While not seen in the wild, issue may show up with a BIOS that reported > CXL root ports via Generic Ports (via a PCI handle in the SRAT entry). > > Fixes: 14a6960b3e92 ("cxl: Add helper function that calculate performance data for downstream ports") > Reported-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > Signed-off-by: Dave Jiang <dave.jiang@intel.com> Looks nice and clean now., So subject to resolution of the philosophy question inline... Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > --- > v3: > - Simplify iteration loop in cxl_endpoint_get_perf_coordinates(). (Jonathan) > --- > drivers/cxl/core/port.c | 33 +++++++++++++++++++++++---------- > 1 file changed, 23 insertions(+), 10 deletions(-) > > diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c > index 6fa273677963..baaaeddae775 100644 > --- a/drivers/cxl/core/port.c > +++ b/drivers/cxl/core/port.c > @@ -2110,6 +2110,20 @@ static void combine_coordinates(struct access_coordinate *c1, > c1->read_latency += c2->read_latency; > } > > +static bool coordinates_invalid(struct access_coordinate *c) > +{ > + if (!c->read_bandwidth && !c->write_bandwidth && > + !c->read_latency && !c->write_latency) > + return true; I'm not sure on logic here. I agree in theory it's possible to have only one coord presented but do we actually want to support that? One of those cases where perhaps Linux should insist on sanity even if the specifications do not. I'd demand them all and flip to coordinates_valid() perhaps? return c->readbandwidth && c->write_bandwidth && c->read_latency && c->write_latency; Maybe there is a dubious argument that a host might not provide bandwidth to the HB if it knows it is way bigger than anything beyond that point... Doubtful.. > + > + return false; > +} > + > +static bool parent_port_is_cxl_root(struct cxl_port *port) > +{ > + return is_cxl_root(to_cxl_port(port->dev.parent)); > +} > + > /** > * cxl_endpoint_get_perf_coordinates - Retrieve performance numbers stored in dports > * of CXL path > @@ -2133,23 +2147,22 @@ int cxl_endpoint_get_perf_coordinates(struct cxl_port *port, > if (!is_cxl_endpoint(port)) > return -EINVAL; > > - dport = iter->parent_dport; > - > /* > - * Exit the loop when the parent port of the current port is cxl root. > - * The iterative loop starts at the endpoint and gathers the > - * latency of the CXL link from the current iter to the next downstream > - * port each iteration. If the parent is cxl root then there is > - * nothing to gather. > + * Exit the loop when the parent port of the current iter port is cxl > + * root. The iterative loop starts at the endpoint and gathers the > + * latency of the CXL link from the current device/port to the connected > + * downstream port each iteration. > */ > - while (!is_cxl_root(to_cxl_port(iter->dev.parent))) { > + do { > + dport = iter->parent_dport; > + if (coordinates_invalid(&dport->coord)) > + return -EINVAL; > combine_coordinates(&c, &dport->coord); > c.write_latency += dport->link_latency; > c.read_latency += dport->link_latency; > > iter = to_cxl_port(iter->dev.parent); > - dport = iter->parent_dport; > - } > + } while (!parent_port_is_cxl_root(iter)); > > /* Get the calculated PCI paths bandwidth */ > pdev = to_pci_dev(port->uport_dev->parent); ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2024-03-07 12:59 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-03-06 17:52 [PATCH v3 1/3] cxl: Remove checking of iter in cxl_endpoint_get_perf_coordinates() Dave Jiang 2024-03-06 17:52 ` [PATCH v3 2/3] cxl: Consolidate dport access_coordinate ->hb_coord and ->sw_coord into ->coord Dave Jiang 2024-03-07 12:53 ` Jonathan Cameron 2024-03-06 17:52 ` [PATCH v3 3/3] cxl: Add checks to access_coordinate calculation to fail missing data Dave Jiang 2024-03-07 12:59 ` Jonathan Cameron
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