* [PATCH v9 0/2] check interleave capability
@ 2024-06-14 8:47 Yao Xingtao
2024-06-14 8:47 ` [PATCH v9 1/2] cxl/region: " Yao Xingtao
2024-06-14 8:47 ` [PATCH v9 2/2] cxl: documentation: add missing files to cxl driver-api Yao Xingtao
0 siblings, 2 replies; 6+ messages in thread
From: Yao Xingtao @ 2024-06-14 8:47 UTC (permalink / raw)
To: dave, jonathan.cameron, dave.jiang, alison.schofield,
vishal.l.verma, ira.weiny, dan.j.williams, jim.harris
Cc: linux-cxl, Yao Xingtao
Currently, the cxl driver does not check the interleave capability of
devices (such as host bridges, switches, cxl_mem, etc.) when creating
a region.
When the driver adds a device to the region and sets its decoder, if the
device does not support the specified interleave ways or interleave
granularity, the device may ignore unsupported bits, causing the
configured decoder to be inconsistent with expectations.
During memory access, the decoder may decode the HPA into an incorrect DPA,
ultimately leading to memory access failure.
Checking the interleave capability of a device early in the process of
adding it to a region can quickly prevent this issue from occurring.
Changes:
V8[8] -> V9:
-- merge cxl_test modification into patch1.
-- append other missing files to kernel-doc and fix the complie warning.
-- optimize the interleave capability check logical.
V7[7] -> V8:
-- drop the redundant check in check_interleave_cap().
-- add cxlmem.h to kernel-doc. (newly add)
-- fixup cxl_test. (newly add)
V6[6] -> V7:
-- update comment.
V5[5] -> V6:
-- fix some typo.
-- update comment.
-- set rc when check failed in cxl_port_attach_region().
V4[4] -> V5:
-- update comment.
-- add nr_targets check while attaching a port to switch.
-- delete passthrough flag and allow all the capabilities for passthrough
decoders.
V3[3] -> V4:
-- update comment.
-- optimize the code.
-- add a passthrough flag to mark the passthrough decoder.
V2[2] -> V3:
-- revert ig_cap_mask to interleave_mask.
-- fix the interleave bits check logical.
V1[1] -> V2:
-- rename interleave_mask to ig_cap_mask.
-- add a check for interleave granularity.
-- update commit.
-- move hdm caps init to parse_hdm_decoder_caps().
[1]
https://lore.kernel.org/linux-cxl/20240401075635.9333-1-yaoxt.fnst@fujitsu.com
[2]
https://lore.kernel.org/linux-cxl/20240403021747.17260-1-yaoxt.fnst@fujitsu.com
[3]
https://lore.kernel.org/linux-cxl/20240409022621.29115-1-yaoxt.fnst@fujitsu.com
[4]
https://lore.kernel.org/linux-cxl/20240422091350.4701-1-yaoxt.fnst@fujitsu.com
[5]
https://lore.kernel.org/linux-cxl/20240524092740.4260-1-yaoxt.fnst@fujitsu.com
[6]
https://lore.kernel.org/linux-cxl/20240611021511.35315-1-yaoxt.fnst@fujitsu.com
[7]
https://lore.kernel.org/linux-cxl/20240612032544.39149-1-yaoxt.fnst@fujitsu.com
[8]
https://lore.kernel.org/linux-cxl/20240614032133.45365-1-yaoxt.fnst@fujitsu.com
Yao Xingtao (2):
cxl/region: check interleave capability
cxl: documentation: add missing files to cxl driver-api
.../driver-api/cxl/memory-devices.rst | 15 ++++
drivers/cxl/core/hdm.c | 13 +++
drivers/cxl/core/region.c | 82 +++++++++++++++++++
drivers/cxl/cxl.h | 2 +
drivers/cxl/cxlmem.h | 21 +++--
tools/testing/cxl/test/cxl.c | 4 +
6 files changed, 132 insertions(+), 5 deletions(-)
--
2.37.3
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v9 1/2] cxl/region: check interleave capability
2024-06-14 8:47 [PATCH v9 0/2] check interleave capability Yao Xingtao
@ 2024-06-14 8:47 ` Yao Xingtao
2024-06-17 16:42 ` Jonathan Cameron
2024-06-14 8:47 ` [PATCH v9 2/2] cxl: documentation: add missing files to cxl driver-api Yao Xingtao
1 sibling, 1 reply; 6+ messages in thread
From: Yao Xingtao @ 2024-06-14 8:47 UTC (permalink / raw)
To: dave, jonathan.cameron, dave.jiang, alison.schofield,
vishal.l.verma, ira.weiny, dan.j.williams, jim.harris
Cc: linux-cxl, Yao Xingtao
Since interleave capability is not verified, if the interleave
capability of a target does not match the region need, committing decoder
should have failed at the device end.
In order to checkout this error as quickly as possible, driver needs
to check the interleave capability of target during attaching it to
region.
Per CXL specification r3.1(8.2.4.20.1 CXL HDM Decoder Capability Register),
bits 11 and 12 indicate the capability to establish interleaving in 3, 6,
12 and 16 ways. If these bits are not set, the target cannot be attached to
a region utilizing such interleave ways.
Additionally, bits 8 and 9 represent the capability of the bits used for
interleaving in the address, Linux tracks this in the cxl_port
interleave_mask.
Per CXL specification r3.1(8.2.4.20.13 Decoder Protection):
eIW means encoded Interleave Ways.
eIG means encoded Interleave Granularity.
in HPA:
if eIW is 0 or 8 (interleave ways: 1, 3), all the bits of HPA are used,
the interleave bits are none, the following check is ignored.
if eIW is less than 8 (interleave ways: 2, 4, 8, 16), the interleave bits
start at bit position eIG + 8 and end at eIG + eIW + 8 - 1.
if eIW is greater than 8 (interleave ways: 6, 12), the interleave bits
start at bit position eIG + 8 and end at eIG + eIW - 1.
if the interleave mask is insufficient to cover the required interleave
bits, the target cannot be attached to the region.
Fixes: 384e624bb211 ("cxl/region: Attach endpoint decoders")
Signed-off-by: Yao Xingtao <yaoxt.fnst@fujitsu.com>
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
---
drivers/cxl/core/hdm.c | 13 ++++++
drivers/cxl/core/region.c | 82 ++++++++++++++++++++++++++++++++++++
drivers/cxl/cxl.h | 2 +
drivers/cxl/cxlmem.h | 10 +++++
tools/testing/cxl/test/cxl.c | 4 ++
5 files changed, 111 insertions(+)
diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
index 784843fa2a22..3df10517a327 100644
--- a/drivers/cxl/core/hdm.c
+++ b/drivers/cxl/core/hdm.c
@@ -52,6 +52,14 @@ int devm_cxl_add_passthrough_decoder(struct cxl_port *port)
struct cxl_dport *dport = NULL;
int single_port_map[1];
unsigned long index;
+ struct cxl_hdm *cxlhdm = dev_get_drvdata(&port->dev);
+
+ /*
+ * Capability checks are moot for passthrough decoders, support
+ * any and all possibilities.
+ */
+ cxlhdm->interleave_mask = ~0U;
+ cxlhdm->iw_cap_mask = ~0UL;
cxlsd = cxl_switch_decoder_alloc(port, 1);
if (IS_ERR(cxlsd))
@@ -79,6 +87,11 @@ static void parse_hdm_decoder_caps(struct cxl_hdm *cxlhdm)
cxlhdm->interleave_mask |= GENMASK(11, 8);
if (FIELD_GET(CXL_HDM_DECODER_INTERLEAVE_14_12, hdm_cap))
cxlhdm->interleave_mask |= GENMASK(14, 12);
+ cxlhdm->iw_cap_mask = BIT(1) | BIT(2) | BIT(4) | BIT(8);
+ if (FIELD_GET(CXL_HDM_DECODER_INTERLEAVE_3_6_12_WAY, hdm_cap))
+ cxlhdm->iw_cap_mask |= BIT(3) | BIT(6) | BIT(12);
+ if (FIELD_GET(CXL_HDM_DECODER_INTERLEAVE_16_WAY, hdm_cap))
+ cxlhdm->iw_cap_mask |= BIT(16);
}
static bool should_emulate_decoders(struct cxl_endpoint_dvsec_info *info)
diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
index 3c2b6144be23..034cc0a90e8f 100644
--- a/drivers/cxl/core/region.c
+++ b/drivers/cxl/core/region.c
@@ -1101,6 +1101,26 @@ static int cxl_port_attach_region(struct cxl_port *port,
}
cxld = cxl_rr->decoder;
+ /*
+ * the number of targets should not exceed the target_count
+ * of the decoder
+ */
+ if (is_switch_decoder(&cxld->dev)) {
+ struct cxl_switch_decoder *cxlsd;
+
+ cxlsd = to_cxl_switch_decoder(&cxld->dev);
+ if (cxl_rr->nr_targets > cxlsd->nr_targets) {
+ dev_dbg(&cxlr->dev,
+ "%s:%s %s add: %s:%s @ %d overflows targets: %d\n",
+ dev_name(port->uport_dev), dev_name(&port->dev),
+ dev_name(&cxld->dev), dev_name(&cxlmd->dev),
+ dev_name(&cxled->cxld.dev), pos,
+ cxlsd->nr_targets);
+ rc = -ENXIO;
+ goto out_erase;
+ }
+ }
+
rc = cxl_rr_ep_add(cxl_rr, cxled);
if (rc) {
dev_dbg(&cxlr->dev,
@@ -1210,6 +1230,50 @@ static int check_last_peer(struct cxl_endpoint_decoder *cxled,
return 0;
}
+static int check_interleave_cap(struct cxl_decoder *cxld, int iw, int ig)
+{
+ struct cxl_port *port = to_cxl_port(cxld->dev.parent);
+ struct cxl_hdm *cxlhdm = dev_get_drvdata(&port->dev);
+ unsigned int interleave_mask;
+ u8 eiw;
+ u16 eig;
+ int high_pos, low_pos;
+
+ if (!test_bit(iw, &cxlhdm->iw_cap_mask))
+ return -ENXIO;
+ /*
+ * Per CXL specification r3.1(8.2.4.20.13 Decoder Protection),
+ * if eiw < 8:
+ * DPAOFFSET[51: eig + 8] = HPAOFFSET[51: eig + 8 + eiw]
+ * DPAOFFSET[eig + 7: 0] = HPAOFFSET[eig + 7: 0]
+ *
+ * when the eiw is 0, all the bits of HPAOFFSET[51: 0] are used, the
+ * interleave bits are none.
+ *
+ * if eiw >= 8:
+ * DPAOFFSET[51: eig + 8] = HPAOFFSET[51: eig + eiw] / 3
+ * DPAOFFSET[eig + 7: 0] = HPAOFFSET[eig + 7: 0]
+ *
+ * when the eiw is 8, all the bits of HPAOFFSET[51: 0] are used, the
+ * interleave bits are none.
+ */
+ ways_to_eiw(iw, &eiw);
+ if (eiw == 0 || eiw == 8)
+ return 0;
+
+ granularity_to_eig(ig, &eig);
+ if (eiw > 8)
+ high_pos = eiw + eig - 1;
+ else
+ high_pos = eiw + eig + 7;
+ low_pos = eig + 8;
+ interleave_mask = GENMASK(high_pos, low_pos);
+ if (interleave_mask & ~cxlhdm->interleave_mask)
+ return -ENXIO;
+
+ return 0;
+}
+
static int cxl_port_setup_targets(struct cxl_port *port,
struct cxl_region *cxlr,
struct cxl_endpoint_decoder *cxled)
@@ -1360,6 +1424,15 @@ static int cxl_port_setup_targets(struct cxl_port *port,
return -ENXIO;
}
} else {
+ rc = check_interleave_cap(cxld, iw, ig);
+ if (rc) {
+ dev_dbg(&cxlr->dev,
+ "%s:%s iw: %d ig: %d is not supported\n",
+ dev_name(port->uport_dev),
+ dev_name(&port->dev), iw, ig);
+ return rc;
+ }
+
cxld->interleave_ways = iw;
cxld->interleave_granularity = ig;
cxld->hpa_range = (struct range) {
@@ -1796,6 +1869,15 @@ static int cxl_region_attach(struct cxl_region *cxlr,
struct cxl_dport *dport;
int rc = -ENXIO;
+ rc = check_interleave_cap(&cxled->cxld, p->interleave_ways,
+ p->interleave_granularity);
+ if (rc) {
+ dev_dbg(&cxlr->dev, "%s iw: %d ig: %d is not supported\n",
+ dev_name(&cxled->cxld.dev), p->interleave_ways,
+ p->interleave_granularity);
+ return rc;
+ }
+
if (cxled->mode != cxlr->mode) {
dev_dbg(&cxlr->dev, "%s region mode: %d mismatch: %d\n",
dev_name(&cxled->cxld.dev), cxlr->mode, cxled->mode);
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 603c0120cff8..d770a00f95e4 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -47,6 +47,8 @@ extern const struct nvdimm_security_ops *cxl_security_ops;
#define CXL_HDM_DECODER_TARGET_COUNT_MASK GENMASK(7, 4)
#define CXL_HDM_DECODER_INTERLEAVE_11_8 BIT(8)
#define CXL_HDM_DECODER_INTERLEAVE_14_12 BIT(9)
+#define CXL_HDM_DECODER_INTERLEAVE_3_6_12_WAY BIT(11)
+#define CXL_HDM_DECODER_INTERLEAVE_16_WAY BIT(12)
#define CXL_HDM_DECODER_CTRL_OFFSET 0x4
#define CXL_HDM_DECODER_ENABLE BIT(1)
#define CXL_HDM_DECODER0_BASE_LOW_OFFSET(i) (0x20 * (i) + 0x10)
diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
index 19aba81cdf13..7806194d2de1 100644
--- a/drivers/cxl/cxlmem.h
+++ b/drivers/cxl/cxlmem.h
@@ -851,11 +851,21 @@ static inline void cxl_mem_active_dec(void)
int cxl_mem_sanitize(struct cxl_memdev *cxlmd, u16 cmd);
+/**
+ * struct cxl_hdm - HDM Decoder registers and cached / decoded capabilities
+ * @regs: mapped registers, see devm_cxl_setup_hdm()
+ * @decoder_count: number of decoders for this port
+ * @target_count: for switch decoders, max downstream port targets
+ * @interleave_mask: interleave granularity capability, see check_interleave_cap()
+ * @iw_cap_mask: bitmask of supported interleave ways, see check_interleave_cap()
+ * @port: mapped cxl_port, see devm_cxl_setup_hdm()
+ */
struct cxl_hdm {
struct cxl_component_regs regs;
unsigned int decoder_count;
unsigned int target_count;
unsigned int interleave_mask;
+ unsigned long iw_cap_mask;
struct cxl_port *port;
};
diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c
index 3482248aa344..90d5afd52dd0 100644
--- a/tools/testing/cxl/test/cxl.c
+++ b/tools/testing/cxl/test/cxl.c
@@ -630,11 +630,15 @@ static struct cxl_hdm *mock_cxl_setup_hdm(struct cxl_port *port,
struct cxl_endpoint_dvsec_info *info)
{
struct cxl_hdm *cxlhdm = devm_kzalloc(&port->dev, sizeof(*cxlhdm), GFP_KERNEL);
+ struct device *dev = &port->dev;
if (!cxlhdm)
return ERR_PTR(-ENOMEM);
cxlhdm->port = port;
+ cxlhdm->interleave_mask = ~0U;
+ cxlhdm->iw_cap_mask = ~0UL;
+ dev_set_drvdata(dev, cxlhdm);
return cxlhdm;
}
--
2.37.3
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v9 2/2] cxl: documentation: add missing files to cxl driver-api
2024-06-14 8:47 [PATCH v9 0/2] check interleave capability Yao Xingtao
2024-06-14 8:47 ` [PATCH v9 1/2] cxl/region: " Yao Xingtao
@ 2024-06-14 8:47 ` Yao Xingtao
2024-06-17 16:43 ` Jonathan Cameron
2024-07-01 15:32 ` Ira Weiny
1 sibling, 2 replies; 6+ messages in thread
From: Yao Xingtao @ 2024-06-14 8:47 UTC (permalink / raw)
To: dave, jonathan.cameron, dave.jiang, alison.schofield,
vishal.l.verma, ira.weiny, dan.j.williams, jim.harris
Cc: linux-cxl, Yao Xingtao
Add the missing files into cxl driver api and fix the compile warning.
Suggested-by: Dan Williams <dan.j.williams@intel.com>
Suggested-by: Alison Schofield <alison.schofield@intel.com>
Signed-off-by: Yao Xingtao <yaoxt.fnst@fujitsu.com>
---
Documentation/driver-api/cxl/memory-devices.rst | 15 +++++++++++++++
drivers/cxl/cxlmem.h | 11 ++++++-----
2 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/Documentation/driver-api/cxl/memory-devices.rst b/Documentation/driver-api/cxl/memory-devices.rst
index 5149ecdc53c7..d732c42526df 100644
--- a/Documentation/driver-api/cxl/memory-devices.rst
+++ b/Documentation/driver-api/cxl/memory-devices.rst
@@ -328,6 +328,12 @@ CXL Memory Device
.. kernel-doc:: drivers/cxl/mem.c
:doc: cxl mem
+.. kernel-doc:: drivers/cxl/cxlmem.h
+ :internal:
+
+.. kernel-doc:: drivers/cxl/core/memdev.c
+ :identifiers:
+
CXL Port
--------
.. kernel-doc:: drivers/cxl/port.c
@@ -341,6 +347,15 @@ CXL Core
.. kernel-doc:: drivers/cxl/cxl.h
:internal:
+.. kernel-doc:: drivers/cxl/core/hdm.c
+ :doc: cxl core hdm
+
+.. kernel-doc:: drivers/cxl/core/hdm.c
+ :identifiers:
+
+.. kernel-doc:: drivers/cxl/core/cdat.c
+ :identifiers:
+
.. kernel-doc:: drivers/cxl/core/port.c
:doc: cxl core
diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
index 7806194d2de1..af8169ccdbc0 100644
--- a/drivers/cxl/cxlmem.h
+++ b/drivers/cxl/cxlmem.h
@@ -395,9 +395,9 @@ enum cxl_devtype {
/**
* struct cxl_dpa_perf - DPA performance property entry
- * @dpa_range - range for DPA address
- * @coord - QoS performance data (i.e. latency, bandwidth)
- * @qos_class - QoS Class cookies
+ * @dpa_range: range for DPA address
+ * @coord: QoS performance data (i.e. latency, bandwidth)
+ * @qos_class: QoS Class cookies
*/
struct cxl_dpa_perf {
struct range dpa_range;
@@ -464,13 +464,14 @@ struct cxl_dev_state {
* @active_persistent_bytes: sum of hard + soft persistent
* @next_volatile_bytes: volatile capacity change pending device reset
* @next_persistent_bytes: persistent capacity change pending device reset
+ * @ram_perf: performance data entry matched to RAM partition
+ * @pmem_perf: performance data entry matched to PMEM partition
* @event: event log driver state
* @poison: poison driver state info
* @security: security driver state info
* @fw: firmware upload / activation state
+ * @mbox_wait: RCU wait for mbox send completely
* @mbox_send: @dev specific transport for transmitting mailbox commands
- * @ram_perf: performance data entry matched to RAM partition
- * @pmem_perf: performance data entry matched to PMEM partition
*
* See CXL 3.0 8.2.9.8.2 Capacity Configuration and Label Storage for
* details on capacity parameters.
--
2.37.3
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v9 1/2] cxl/region: check interleave capability
2024-06-14 8:47 ` [PATCH v9 1/2] cxl/region: " Yao Xingtao
@ 2024-06-17 16:42 ` Jonathan Cameron
0 siblings, 0 replies; 6+ messages in thread
From: Jonathan Cameron @ 2024-06-17 16:42 UTC (permalink / raw)
To: Yao Xingtao
Cc: dave, dave.jiang, alison.schofield, vishal.l.verma, ira.weiny,
dan.j.williams, jim.harris, linux-cxl
On Fri, 14 Jun 2024 04:47:54 -0400
Yao Xingtao <yaoxt.fnst@fujitsu.com> wrote:
> Since interleave capability is not verified, if the interleave
> capability of a target does not match the region need, committing decoder
> should have failed at the device end.
>
> In order to checkout this error as quickly as possible, driver needs
> to check the interleave capability of target during attaching it to
> region.
>
> Per CXL specification r3.1(8.2.4.20.1 CXL HDM Decoder Capability Register),
> bits 11 and 12 indicate the capability to establish interleaving in 3, 6,
> 12 and 16 ways. If these bits are not set, the target cannot be attached to
> a region utilizing such interleave ways.
>
> Additionally, bits 8 and 9 represent the capability of the bits used for
> interleaving in the address, Linux tracks this in the cxl_port
> interleave_mask.
>
> Per CXL specification r3.1(8.2.4.20.13 Decoder Protection):
> eIW means encoded Interleave Ways.
> eIG means encoded Interleave Granularity.
>
> in HPA:
> if eIW is 0 or 8 (interleave ways: 1, 3), all the bits of HPA are used,
> the interleave bits are none, the following check is ignored.
>
> if eIW is less than 8 (interleave ways: 2, 4, 8, 16), the interleave bits
> start at bit position eIG + 8 and end at eIG + eIW + 8 - 1.
>
> if eIW is greater than 8 (interleave ways: 6, 12), the interleave bits
> start at bit position eIG + 8 and end at eIG + eIW - 1.
>
> if the interleave mask is insufficient to cover the required interleave
> bits, the target cannot be attached to the region.
>
> Fixes: 384e624bb211 ("cxl/region: Attach endpoint decoders")
> Signed-off-by: Yao Xingtao <yaoxt.fnst@fujitsu.com>
> Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Trivial comment inline. Either way
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>
> static bool should_emulate_decoders(struct cxl_endpoint_dvsec_info *info)
> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> index 3c2b6144be23..034cc0a90e8f 100644
> --- a/drivers/cxl/core/region.c
> +++ b/drivers/cxl/core/region.c
>
> +static int check_interleave_cap(struct cxl_decoder *cxld, int iw, int ig)
> +{
> + struct cxl_port *port = to_cxl_port(cxld->dev.parent);
> + struct cxl_hdm *cxlhdm = dev_get_drvdata(&port->dev);
> + unsigned int interleave_mask;
> + u8 eiw;
> + u16 eig;
> + int high_pos, low_pos;
> +
Possibly reorder to be reverse xmas tree.
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v9 2/2] cxl: documentation: add missing files to cxl driver-api
2024-06-14 8:47 ` [PATCH v9 2/2] cxl: documentation: add missing files to cxl driver-api Yao Xingtao
@ 2024-06-17 16:43 ` Jonathan Cameron
2024-07-01 15:32 ` Ira Weiny
1 sibling, 0 replies; 6+ messages in thread
From: Jonathan Cameron @ 2024-06-17 16:43 UTC (permalink / raw)
To: Yao Xingtao
Cc: dave, dave.jiang, alison.schofield, vishal.l.verma, ira.weiny,
dan.j.williams, jim.harris, linux-cxl
On Fri, 14 Jun 2024 04:47:55 -0400
Yao Xingtao <yaoxt.fnst@fujitsu.com> wrote:
> Add the missing files into cxl driver api and fix the compile warning.
>
> Suggested-by: Dan Williams <dan.j.williams@intel.com>
> Suggested-by: Alison Schofield <alison.schofield@intel.com>
> Signed-off-by: Yao Xingtao <yaoxt.fnst@fujitsu.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v9 2/2] cxl: documentation: add missing files to cxl driver-api
2024-06-14 8:47 ` [PATCH v9 2/2] cxl: documentation: add missing files to cxl driver-api Yao Xingtao
2024-06-17 16:43 ` Jonathan Cameron
@ 2024-07-01 15:32 ` Ira Weiny
1 sibling, 0 replies; 6+ messages in thread
From: Ira Weiny @ 2024-07-01 15:32 UTC (permalink / raw)
To: Yao Xingtao, dave, jonathan.cameron, dave.jiang, alison.schofield,
vishal.l.verma, ira.weiny, dan.j.williams, jim.harris
Cc: linux-cxl, Yao Xingtao
Yao Xingtao wrote:
> Add the missing files into cxl driver api and fix the compile warning.
>
> Suggested-by: Dan Williams <dan.j.williams@intel.com>
> Suggested-by: Alison Schofield <alison.schofield@intel.com>
> Signed-off-by: Yao Xingtao <yaoxt.fnst@fujitsu.com>
Patch looks good. But I think linux-doc should have been CC'ed as well.
Also, This should have been sent as a stand alone patch so Dave can pick
it up separate from the interleave fix. I think he can pick it out from
here this time.
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
> ---
> Documentation/driver-api/cxl/memory-devices.rst | 15 +++++++++++++++
> drivers/cxl/cxlmem.h | 11 ++++++-----
> 2 files changed, 21 insertions(+), 5 deletions(-)
>
> diff --git a/Documentation/driver-api/cxl/memory-devices.rst b/Documentation/driver-api/cxl/memory-devices.rst
> index 5149ecdc53c7..d732c42526df 100644
> --- a/Documentation/driver-api/cxl/memory-devices.rst
> +++ b/Documentation/driver-api/cxl/memory-devices.rst
> @@ -328,6 +328,12 @@ CXL Memory Device
> .. kernel-doc:: drivers/cxl/mem.c
> :doc: cxl mem
>
> +.. kernel-doc:: drivers/cxl/cxlmem.h
> + :internal:
> +
> +.. kernel-doc:: drivers/cxl/core/memdev.c
> + :identifiers:
> +
> CXL Port
> --------
> .. kernel-doc:: drivers/cxl/port.c
> @@ -341,6 +347,15 @@ CXL Core
> .. kernel-doc:: drivers/cxl/cxl.h
> :internal:
>
> +.. kernel-doc:: drivers/cxl/core/hdm.c
> + :doc: cxl core hdm
> +
> +.. kernel-doc:: drivers/cxl/core/hdm.c
> + :identifiers:
> +
> +.. kernel-doc:: drivers/cxl/core/cdat.c
> + :identifiers:
> +
> .. kernel-doc:: drivers/cxl/core/port.c
> :doc: cxl core
>
> diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
> index 7806194d2de1..af8169ccdbc0 100644
> --- a/drivers/cxl/cxlmem.h
> +++ b/drivers/cxl/cxlmem.h
> @@ -395,9 +395,9 @@ enum cxl_devtype {
>
> /**
> * struct cxl_dpa_perf - DPA performance property entry
> - * @dpa_range - range for DPA address
> - * @coord - QoS performance data (i.e. latency, bandwidth)
> - * @qos_class - QoS Class cookies
> + * @dpa_range: range for DPA address
> + * @coord: QoS performance data (i.e. latency, bandwidth)
> + * @qos_class: QoS Class cookies
> */
> struct cxl_dpa_perf {
> struct range dpa_range;
> @@ -464,13 +464,14 @@ struct cxl_dev_state {
> * @active_persistent_bytes: sum of hard + soft persistent
> * @next_volatile_bytes: volatile capacity change pending device reset
> * @next_persistent_bytes: persistent capacity change pending device reset
> + * @ram_perf: performance data entry matched to RAM partition
> + * @pmem_perf: performance data entry matched to PMEM partition
> * @event: event log driver state
> * @poison: poison driver state info
> * @security: security driver state info
> * @fw: firmware upload / activation state
> + * @mbox_wait: RCU wait for mbox send completely
> * @mbox_send: @dev specific transport for transmitting mailbox commands
> - * @ram_perf: performance data entry matched to RAM partition
> - * @pmem_perf: performance data entry matched to PMEM partition
> *
> * See CXL 3.0 8.2.9.8.2 Capacity Configuration and Label Storage for
> * details on capacity parameters.
> --
> 2.37.3
>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2024-07-01 15:33 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-06-14 8:47 [PATCH v9 0/2] check interleave capability Yao Xingtao
2024-06-14 8:47 ` [PATCH v9 1/2] cxl/region: " Yao Xingtao
2024-06-17 16:42 ` Jonathan Cameron
2024-06-14 8:47 ` [PATCH v9 2/2] cxl: documentation: add missing files to cxl driver-api Yao Xingtao
2024-06-17 16:43 ` Jonathan Cameron
2024-07-01 15:32 ` Ira Weiny
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox