[PATCH v17 0/2] Export cxl1.1 device link status register value to pci device sysfs.

[PATCH v17 0/2] Export cxl1.1 device link status register value to pci device sysfs.

[Kobayashi,Daisuke]

CXL devices are extensions of PCIe. Therefore, from CXL2.0 onwards,
the link status can be output in the same way as traditional PCIe.
However, unlike devices from CXL2.0 onwards, CXL1.1 requires a
different method to obtain the link status from traditional PCIe.
This is because the link status of the CXL1.1 device is not mapped
in the configuration space (as per cxl3.0 specification 8.1).
Instead, the configuration space containing the link status is mapped
to the memory mapped register region (as per cxl3.0 specification 8.2,
Table 8-18). Therefore, the current lspci has a problem where it does
not display the link status of the CXL1.1 device. 
Solve these issues with sysfs attributes to export the status
registers hidden in the RCRB.

The procedure is as follows:
First, obtain the RCRB address within the cxl driver, then access 
the configuration space. Next, output the link status information from
the configuration space to sysfs. Ultimately, the expectation is that
this sysfs file will be consumed by PCI user tools to utilize link status
information.

This patch series relies on the functions defined in the following patches.
https://lore.kernel.org/linux-cxl/20240830013138.2256244-1-ming4.li@intel.com/

Changes
v1[1] -> v2:
- Modified to perform rcrb access within the CXL driver.
- Added new attributes to the sysfs of the PCI device.
- Output the link status information to the sysfs of the PCI device.
- Retrieve information from sysfs as the source when displaying information in lspci.

v2[2] -> v3:
- Fix unnecessary initialization and wrong types (Bjohn).
- Create a helper function for getting a PCIe capability offset (Bjohn).
- Move platform-specific implementation to the lib directory in pciutils (Martin).

v3[3] -> v4:
- RCRB register values are read once and cached.
- Added a new attribute to the sysfs of the PCI device.
- Separate lspci implementation from this patch.

v4[4] -> v5:
- Use macros for bitwise operations
- Fix RCRB access to use cxl_memdev

v5[5] -> v6:
- Add and use masks for RCRB register values

v6[6] -> v7:
- Fix comments on white space inline

v7[7] -> v8:
- Change the cache value to offset
- Access memory map area in rcd_*_show() functions

v8[8] -> v9:
- Map the pcie cap in for all the time the driver is bound to the device.
- Add mapping the pcie cap in cxl_rcd_component_reg_phys().

v9[9] -> v10:
- Change a utility function for getting PCIe capability.
- Fix tab alignment issue, error handling, and apply suggestions from Jonathan.

v10[10] -> v11:
- Add functions to have one function do only one thing.
- Add a size parameter to utility function arguments and consolidated them into one.

v11[11] -> v12:
- Fix the error handling in cxl_pci_setup_regs().
- Fix and clean up some details.

v12[12] -> v13:
- Fix and clean up some details.

v13[13] -> v14:
- Fix and clean up some details.

v14[14] -> v15:
- Change dport lookup to be done only once.
- Fix the visibility of cxl_rcrb_to_linkcap().

v15[15] -> v16:
- Fix the port leak bug by introduce a new scope-based-free handler
- Improve the variable names.

v16[16] -> v17:
- Change used function for making struct cxl_port *port

[1]
https://lore.kernel.org/linux-cxl/20231220050738.178481-1-kobayashi.da-06@fujitsu.com/
[2]
https://lore.kernel.org/linux-cxl/20240227083313.87699-1-kobayashi.da-06@fujitsu.com/
[3]
https://lore.kernel.org/linux-cxl/20240312080559.14904-1-kobayashi.da-06@fujitsu.com/
[4]
https://lore.kernel.org/linux-cxl/20240409073528.13214-1-kobayashi.da-06@fujitsu.com/
[5]
https://lore.kernel.org/linux-cxl/20240412070715.16160-1-kobayashi.da-06@fujitsu.com/
[6]
https://lore.kernel.org/linux-cxl/20240424050102.26788-1-kobayashi.da-06@fujitsu.com/
[7]
https://lore.kernel.org/linux-cxl/20240510073710.98953-1-kobayashi.da-06@fujitsu.com/
[8]
https://lore.kernel.org/linux-cxl/20240606074814.5633-1-kobayashi.da-06@fujitsu.com/
[9]
https://lore.kernel.org/linux-cxl/20240610082222.22772-1-kobayashi.da-06@fujitsu.com/
[10]
https://lore.kernel.org/linux-cxl/20240611055254.61203-1-kobayashi.da-06@fujitsu.com/
[11]
https://lore.kernel.org/linux-cxl/20240612075940.92500-1-kobayashi.da-06@fujitsu.com/
[12]
https://lore.kernel.org/linux-cxl/20240614045611.58658-1-kobayashi.da-06@fujitsu.com/
[13]
https://lore.kernel.org/linux-cxl/20240617043702.62028-1-kobayashi.da-06@fujitsu.com/
[14]
https://lore.kernel.org/linux-cxl/20240618042941.96893-1-kobayashi.da-06@fujitsu.com/
[15]
https://lore.kernel.org/linux-cxl/20240716042540.89639-1-kobayashi.da-06@fujitsu.com/
[16]
https://lore.kernel.org/linux-cxl/20240815005510.220835-1-kobayashi.da-06@fujitsu.com/

Kobayashi,Daisuke (2):
  cxl/core/regs: Add rcd_pcie_cap initialization
  cxl/pci: Add sysfs attribute for CXL 1.1 device link status

 drivers/cxl/core/core.h |   5 ++
 drivers/cxl/core/regs.c |  56 ++++++++++++++++++++
 drivers/cxl/cxl.h       |   9 ++++
 drivers/cxl/pci.c       | 110 +++++++++++++++++++++++++++++++++++-----
 4 files changed, 167 insertions(+), 13 deletions(-)

-- 
2.45.0

[PATCH v17 1/2] cxl/core/regs: Add rcd_pcie_cap initialization

[Kobayashi,Daisuke]

Add rcd_pcie_cap and its initialization to cache the offset of cxl1.1 
device link status information. By caching it, avoid the walking 
memory map area to find the offset when output the register value.

Given that this solution involves port lookups via cxl_pci_find_port()
and multiple exit paths where that reference needs to be dropped,
introduce a new put_cxl_root() scope-based-free handler.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: "Kobayashi,Daisuke" <kobayashi.da-06@fujitsu.com>
---
 drivers/cxl/core/core.h |  5 ++++
 drivers/cxl/core/regs.c | 56 +++++++++++++++++++++++++++++++++++++++++
 drivers/cxl/cxl.h       |  9 +++++++
 drivers/cxl/pci.c       | 32 +++++++++++++----------
 4 files changed, 89 insertions(+), 13 deletions(-)

diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h
index 3b64fb1b9ed0..95d94ec14eb6 100644
--- a/drivers/cxl/core/core.h
+++ b/drivers/cxl/core/core.h
@@ -75,6 +75,11 @@ resource_size_t __rcrb_to_component(struct device *dev,
 				    enum cxl_rcrb which);
 u16 cxl_rcrb_to_aer(struct device *dev, resource_size_t rcrb);
 
+#define PCI_RCRB_CAP_LIST_ID_MASK	GENMASK(7, 0)
+#define PCI_RCRB_CAP_HDR_ID_MASK	GENMASK(7, 0)
+#define PCI_RCRB_CAP_HDR_NEXT_MASK	GENMASK(15, 8)
+#define PCI_CAP_EXP_SIZEOF		0x3c
+
 extern struct rw_semaphore cxl_dpa_rwsem;
 extern struct rw_semaphore cxl_region_rwsem;
 
diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
index 372786f80955..b1ab0d9bcbcb 100644
--- a/drivers/cxl/core/regs.c
+++ b/drivers/cxl/core/regs.c
@@ -505,6 +505,62 @@ u16 cxl_rcrb_to_aer(struct device *dev, resource_size_t rcrb)
 	return offset;
 }
 
+static resource_size_t cxl_rcrb_to_linkcap(struct device *dev, struct cxl_dport *dport)
+{
+	resource_size_t rcrb = dport->rcrb.base;
+	void __iomem *addr;
+	u32 cap_hdr;
+	u16 offset;
+
+	if (!request_mem_region(rcrb, SZ_4K, "CXL RCRB"))
+		return CXL_RESOURCE_NONE;
+
+	addr = ioremap(rcrb, SZ_4K);
+	if (!addr) {
+		dev_err(dev, "Failed to map region %pr\n", addr);
+		release_mem_region(rcrb, SZ_4K);
+		return CXL_RESOURCE_NONE;
+	}
+
+	offset = FIELD_GET(PCI_RCRB_CAP_LIST_ID_MASK, readw(addr + PCI_CAPABILITY_LIST));
+	cap_hdr = readl(addr + offset);
+	while ((FIELD_GET(PCI_RCRB_CAP_HDR_ID_MASK, cap_hdr)) != PCI_CAP_ID_EXP) {
+		offset = FIELD_GET(PCI_RCRB_CAP_HDR_NEXT_MASK, cap_hdr);
+		if (offset == 0 || offset > SZ_4K) {
+			offset = 0;
+			break;
+		}
+		cap_hdr = readl(addr + offset);
+	}
+
+	iounmap(addr);
+	release_mem_region(rcrb, SZ_4K);
+	if (!offset)
+		return CXL_RESOURCE_NONE;
+
+	return offset;
+}
+
+int cxl_dport_map_rcd_linkcap(struct pci_dev *pdev, struct cxl_dport *dport)
+{
+	void __iomem *dport_pcie_cap = NULL;
+	resource_size_t pos;
+	struct cxl_rcrb_info *ri;
+
+	ri = &dport->rcrb;
+	pos = cxl_rcrb_to_linkcap(&pdev->dev, dport);
+	if (pos == CXL_RESOURCE_NONE)
+		return -ENXIO;
+
+	dport_pcie_cap = devm_cxl_iomap_block(&pdev->dev,
+					      ri->base + pos,
+					      PCI_CAP_EXP_SIZEOF);
+	dport->regs.rcd_pcie_cap = dport_pcie_cap;
+
+	return 0;
+}
+EXPORT_SYMBOL_NS_GPL(cxl_dport_map_rcd_linkcap, CXL);
+
 resource_size_t __rcrb_to_component(struct device *dev, struct cxl_rcrb_info *ri,
 				    enum cxl_rcrb which)
 {
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 003feebab79b..839c5a20cc33 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -230,6 +230,14 @@ struct cxl_regs {
 	struct_group_tagged(cxl_rch_regs, rch_regs,
 		void __iomem *dport_aer;
 	);
+
+	/*
+	 * RCD upstream port specific PCIe cap register
+	 * @pcie_cap: CXL 3.0 8.2.1.2 RCD Upstream Port RCRB
+	 */
+	struct_group_tagged(cxl_rcd_regs, rcd_regs,
+		void __iomem *rcd_pcie_cap;
+	);
 };
 
 struct cxl_reg_map {
@@ -299,6 +307,7 @@ int cxl_setup_regs(struct cxl_register_map *map);
 struct cxl_dport;
 resource_size_t cxl_rcd_component_reg_phys(struct device *dev,
 					   struct cxl_dport *dport);
+int cxl_dport_map_rcd_linkcap(struct pci_dev *pdev, struct cxl_dport *dport);
 
 #define CXL_RESOURCE_NONE ((resource_size_t) -1)
 #define CXL_TARGET_STRLEN 20
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index 2ff361e756d6..5aebb0ab3dd1 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -471,10 +471,9 @@ static bool is_cxl_restricted(struct pci_dev *pdev)
 }
 
 static int cxl_rcrb_get_comp_regs(struct pci_dev *pdev,
-				  struct cxl_register_map *map)
+				  struct cxl_register_map *map,
+				  struct cxl_dport *dport)
 {
-	struct cxl_port *port;
-	struct cxl_dport *dport;
 	resource_size_t component_reg_phys;
 
 	*map = (struct cxl_register_map) {
@@ -482,14 +481,8 @@ static int cxl_rcrb_get_comp_regs(struct pci_dev *pdev,
 		.resource = CXL_RESOURCE_NONE,
 	};
 
-	port = cxl_pci_find_port(pdev, &dport);
-	if (!port)
-		return -EPROBE_DEFER;
-
 	component_reg_phys = cxl_rcd_component_reg_phys(&pdev->dev, dport);
 
-	put_device(&port->dev);
-
 	if (component_reg_phys == CXL_RESOURCE_NONE)
 		return -ENXIO;
 
@@ -512,11 +505,24 @@ static int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
 	 * is an RCH and try to extract the Component Registers from
 	 * an RCRB.
 	 */
-	if (rc && type == CXL_REGLOC_RBI_COMPONENT && is_cxl_restricted(pdev))
-		rc = cxl_rcrb_get_comp_regs(pdev, map);
-
-	if (rc)
+	if (rc && type == CXL_REGLOC_RBI_COMPONENT && is_cxl_restricted(pdev)) {
+		struct cxl_dport *dport;
+		struct cxl_port *port __free(put_cxl_port) =
+			cxl_pci_find_port(pdev, &dport);
+		if (!port)
+			return -EPROBE_DEFER;
+
+		rc = cxl_rcrb_get_comp_regs(pdev, map, dport);
+		if (rc)
+			return rc;
+
+		rc = cxl_dport_map_rcd_linkcap(pdev, dport);
+		if (rc)
+			return rc;
+
+	} else if (rc) {
 		return rc;
+	}
 
 	return cxl_setup_regs(map);
 }
-- 
2.45.0

[PATCH v17 2/2] cxl/pci: Add sysfs attribute for CXL 1.1 device link status

[Kobayashi,Daisuke]

Add sysfs attribute for CXL 1.1 device link status to the cxl pci device.

In CXL1.1, the link status of the device is included in the RCRB mapped to
the memory mapped register area. Critically, that arrangement makes the
link status and control registers invisible to existing PCI user tooling.

Export those registers via sysfs with the expectation that PCI user
tooling will alternatively look for these sysfs files when attempting to
access to these CXL 1.1 endpoints registers.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: "Kobayashi,Daisuke" <kobayashi.da-06@fujitsu.com>
---
 drivers/cxl/pci.c | 78 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 78 insertions(+)

diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index 5aebb0ab3dd1..09a3c111413a 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -792,6 +792,83 @@ static int cxl_event_config(struct pci_host_bridge *host_bridge,
 	return 0;
 }
 
+static ssize_t rcd_pcie_cap_emit(struct device *dev, u16 offset, char *buf, size_t width)
+{
+	struct cxl_dev_state *cxlds = dev_get_drvdata(dev);
+	struct cxl_memdev *cxlmd = cxlds->cxlmd;
+	struct device *root_dev;
+	struct cxl_dport *dport;
+	struct cxl_port *root __free(put_cxl_port) =
+		cxl_mem_find_port(cxlmd, &dport);
+
+	if (!root)
+		return -ENXIO;
+
+	root_dev = root->uport_dev;
+	if (!root_dev)
+		return -ENXIO;
+
+	guard(device)(root_dev);
+	if (!root_dev->driver)
+		return -ENXIO;
+
+	switch (width) {
+	case 2:
+		return sysfs_emit(buf, "%#x\n",
+				  readw(dport->regs.rcd_pcie_cap + offset));
+	case 4:
+		return sysfs_emit(buf, "%#x\n",
+				  readl(dport->regs.rcd_pcie_cap + offset));
+	default:
+		return -EINVAL;
+	}
+}
+
+static ssize_t rcd_link_cap_show(struct device *dev,
+				 struct device_attribute *attr, char *buf)
+{
+	return rcd_pcie_cap_emit(dev, PCI_EXP_LNKCAP, buf, sizeof(u32));
+}
+static DEVICE_ATTR_RO(rcd_link_cap);
+
+static ssize_t rcd_link_ctrl_show(struct device *dev,
+				  struct device_attribute *attr, char *buf)
+{
+	return rcd_pcie_cap_emit(dev, PCI_EXP_LNKCTL, buf, sizeof(u16));
+}
+static DEVICE_ATTR_RO(rcd_link_ctrl);
+
+static ssize_t rcd_link_status_show(struct device *dev,
+				    struct device_attribute *attr, char *buf)
+{
+	return rcd_pcie_cap_emit(dev, PCI_EXP_LNKSTA, buf, sizeof(u16));
+}
+static DEVICE_ATTR_RO(rcd_link_status);
+
+static struct attribute *cxl_rcd_attrs[] = {
+	&dev_attr_rcd_link_cap.attr,
+	&dev_attr_rcd_link_ctrl.attr,
+	&dev_attr_rcd_link_status.attr,
+	NULL
+};
+
+static umode_t cxl_rcd_visible(struct kobject *kobj, struct attribute *a, int n)
+{
+	struct device *dev = kobj_to_dev(kobj);
+	struct pci_dev *pdev = to_pci_dev(dev);
+
+	if (is_cxl_restricted(pdev))
+		return a->mode;
+
+	return 0;
+}
+
+static struct attribute_group cxl_rcd_group = {
+	.attrs = cxl_rcd_attrs,
+	.is_visible = cxl_rcd_visible,
+};
+__ATTRIBUTE_GROUPS(cxl_rcd);
+
 static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 {
 	struct pci_host_bridge *host_bridge = pci_find_host_bridge(pdev->bus);
@@ -975,6 +1052,7 @@ static struct pci_driver cxl_pci_driver = {
 	.id_table		= cxl_mem_pci_tbl,
 	.probe			= cxl_pci_probe,
 	.err_handler		= &cxl_error_handlers,
+	.dev_groups		= cxl_rcd_groups,
 	.driver	= {
 		.probe_type	= PROBE_PREFER_ASYNCHRONOUS,
 	},
-- 
2.45.0

Re: [PATCH v17 1/2] cxl/core/regs: Add rcd_pcie_cap initialization

[kernel test robot]

Hi Kobayashi,Daisuke,

kernel test robot noticed the following build errors:

[auto build test ERROR on cxl/next]
[also build test ERROR on linus/master cxl/pending v6.11-rc6 next-20240903]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Kobayashi-Daisuke/cxl-core-regs-Add-rcd_pcie_cap-initialization/20240903-110023
base:   https://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl.git next
patch link:    https://lore.kernel.org/r/20240903025915.270521-2-kobayashi.da-06%40fujitsu.com
patch subject: [PATCH v17 1/2] cxl/core/regs: Add rcd_pcie_cap initialization
config: alpha-allyesconfig (https://download.01.org/0day-ci/archive/20240904/202409040011.kaajNuCb-lkp@intel.com/config)
compiler: alpha-linux-gcc (GCC) 13.3.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240904/202409040011.kaajNuCb-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202409040011.kaajNuCb-lkp@intel.com/

All errors (new ones prefixed by >>):

   drivers/cxl/pci.c: In function 'cxl_pci_setup_regs':
>> drivers/cxl/pci.c:511:25: error: cleanup argument not a function
     511 |                         cxl_pci_find_port(pdev, &dport);
         |                         ^~~~~~~~~~~~~~~~~


vim +511 drivers/cxl/pci.c

   495	
   496	static int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
   497				      struct cxl_register_map *map)
   498	{
   499		int rc;
   500	
   501		rc = cxl_find_regblock(pdev, type, map);
   502	
   503		/*
   504		 * If the Register Locator DVSEC does not exist, check if it
   505		 * is an RCH and try to extract the Component Registers from
   506		 * an RCRB.
   507		 */
   508		if (rc && type == CXL_REGLOC_RBI_COMPONENT && is_cxl_restricted(pdev)) {
   509			struct cxl_dport *dport;
   510			struct cxl_port *port __free(put_cxl_port) =
 > 511				cxl_pci_find_port(pdev, &dport);
   512			if (!port)
   513				return -EPROBE_DEFER;
   514	
   515			rc = cxl_rcrb_get_comp_regs(pdev, map, dport);
   516			if (rc)
   517				return rc;
   518	
   519			rc = cxl_dport_map_rcd_linkcap(pdev, dport);
   520			if (rc)
   521				return rc;
   522	
   523		} else if (rc) {
   524			return rc;
   525		}
   526	
   527		return cxl_setup_regs(map);
   528	}
   529	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH v17 1/2] cxl/core/regs: Add rcd_pcie_cap initialization

[kernel test robot]

Hi Kobayashi,Daisuke,

kernel test robot noticed the following build errors:

[auto build test ERROR on cxl/next]
[also build test ERROR on linus/master cxl/pending v6.11-rc6 next-20240903]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Kobayashi-Daisuke/cxl-core-regs-Add-rcd_pcie_cap-initialization/20240903-110023
base:   https://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl.git next
patch link:    https://lore.kernel.org/r/20240903025915.270521-2-kobayashi.da-06%40fujitsu.com
patch subject: [PATCH v17 1/2] cxl/core/regs: Add rcd_pcie_cap initialization
config: x86_64-randconfig-001-20240903 (https://download.01.org/0day-ci/archive/20240904/202409040010.afyGcWUe-lkp@intel.com/config)
compiler: clang version 18.1.5 (https://github.com/llvm/llvm-project 617a15a9eac96088ae5e9134248d8236e34b91b1)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240904/202409040010.afyGcWUe-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202409040010.afyGcWUe-lkp@intel.com/

All errors (new ones prefixed by >>):

>> drivers/cxl/pci.c:510:25: error: use of undeclared identifier '__free_put_cxl_port'; did you mean '__free_put_cxl_root'?
     510 |                 struct cxl_port *port __free(put_cxl_port) =
         |                                       ^
   include/linux/cleanup.h:64:33: note: expanded from macro '__free'
      64 | #define __free(_name)   __cleanup(__free_##_name)
         |                                   ^
   <scratch space>:28:1: note: expanded from here
      28 | __free_put_cxl_port
         | ^
   drivers/cxl/cxl.h:752:1: note: '__free_put_cxl_root' declared here
     752 | DEFINE_FREE(put_cxl_root, struct cxl_root *, if (_T) put_cxl_root(_T))
         | ^
   include/linux/cleanup.h:62:21: note: expanded from macro 'DEFINE_FREE'
      62 |         static inline void __free_##_name(void *p) { _type _T = *(_type *)p; _free; }
         |                            ^
   <scratch space>:64:1: note: expanded from here
      64 | __free_put_cxl_root
         | ^
   1 error generated.


vim +510 drivers/cxl/pci.c

   495	
   496	static int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
   497				      struct cxl_register_map *map)
   498	{
   499		int rc;
   500	
   501		rc = cxl_find_regblock(pdev, type, map);
   502	
   503		/*
   504		 * If the Register Locator DVSEC does not exist, check if it
   505		 * is an RCH and try to extract the Component Registers from
   506		 * an RCRB.
   507		 */
   508		if (rc && type == CXL_REGLOC_RBI_COMPONENT && is_cxl_restricted(pdev)) {
   509			struct cxl_dport *dport;
 > 510			struct cxl_port *port __free(put_cxl_port) =
   511				cxl_pci_find_port(pdev, &dport);
   512			if (!port)
   513				return -EPROBE_DEFER;
   514	
   515			rc = cxl_rcrb_get_comp_regs(pdev, map, dport);
   516			if (rc)
   517				return rc;
   518	
   519			rc = cxl_dport_map_rcd_linkcap(pdev, dport);
   520			if (rc)
   521				return rc;
   522	
   523		} else if (rc) {
   524			return rc;
   525		}
   526	
   527		return cxl_setup_regs(map);
   528	}
   529	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

RE: [PATCH v17 0/2] Export cxl1.1 device link status register value to pci device sysfs.

[Daisuke Kobayashi (Fujitsu)]

Hi, Dan. Could you please review this patch?
I think I've fixed the issues you mentioned.

Thank you.

Kobayashi Daisuke wrote:
> Subject: [PATCH v17 0/2] Export cxl1.1 device link status register value to pci
> device sysfs.
> 
> CXL devices are extensions of PCIe. Therefore, from CXL2.0 onwards, the link
> status can be output in the same way as traditional PCIe.
> However, unlike devices from CXL2.0 onwards, CXL1.1 requires a different
> method to obtain the link status from traditional PCIe.
> This is because the link status of the CXL1.1 device is not mapped in the
> configuration space (as per cxl3.0 specification 8.1).
> Instead, the configuration space containing the link status is mapped to the
> memory mapped register region (as per cxl3.0 specification 8.2, Table 8-18).
> Therefore, the current lspci has a problem where it does not display the link
> status of the CXL1.1 device.
> Solve these issues with sysfs attributes to export the status registers hidden in
> the RCRB.
> 
> The procedure is as follows:
> First, obtain the RCRB address within the cxl driver, then access the
> configuration space. Next, output the link status information from the
> configuration space to sysfs. Ultimately, the expectation is that this sysfs file
> will be consumed by PCI user tools to utilize link status information.
> 
> This patch series relies on the functions defined in the following patches.
> https://lore.kernel.org/linux-cxl/20240830013138.2256244-1-ming4.li@intel.c
> om/
> 
> Changes
> v1[1] -> v2:
> - Modified to perform rcrb access within the CXL driver.
> - Added new attributes to the sysfs of the PCI device.
> - Output the link status information to the sysfs of the PCI device.
> - Retrieve information from sysfs as the source when displaying information in
> lspci.
> 
> v2[2] -> v3:
> - Fix unnecessary initialization and wrong types (Bjohn).
> - Create a helper function for getting a PCIe capability offset (Bjohn).
> - Move platform-specific implementation to the lib directory in pciutils
> (Martin).
> 
> v3[3] -> v4:
> - RCRB register values are read once and cached.
> - Added a new attribute to the sysfs of the PCI device.
> - Separate lspci implementation from this patch.
> 
> v4[4] -> v5:
> - Use macros for bitwise operations
> - Fix RCRB access to use cxl_memdev
> 
> v5[5] -> v6:
> - Add and use masks for RCRB register values
> 
> v6[6] -> v7:
> - Fix comments on white space inline
> 
> v7[7] -> v8:
> - Change the cache value to offset
> - Access memory map area in rcd_*_show() functions
> 
> v8[8] -> v9:
> - Map the pcie cap in for all the time the driver is bound to the device.
> - Add mapping the pcie cap in cxl_rcd_component_reg_phys().
> 
> v9[9] -> v10:
> - Change a utility function for getting PCIe capability.
> - Fix tab alignment issue, error handling, and apply suggestions from Jonathan.
> 
> v10[10] -> v11:
> - Add functions to have one function do only one thing.
> - Add a size parameter to utility function arguments and consolidated them into
> one.
> 
> v11[11] -> v12:
> - Fix the error handling in cxl_pci_setup_regs().
> - Fix and clean up some details.
> 
> v12[12] -> v13:
> - Fix and clean up some details.
> 
> v13[13] -> v14:
> - Fix and clean up some details.
> 
> v14[14] -> v15:
> - Change dport lookup to be done only once.
> - Fix the visibility of cxl_rcrb_to_linkcap().
> 
> v15[15] -> v16:
> - Fix the port leak bug by introduce a new scope-based-free handler
> - Improve the variable names.
> 
> v16[16] -> v17:
> - Change used function for making struct cxl_port *port
> 
> [1]
> https://lore.kernel.org/linux-cxl/20231220050738.178481-1-kobayashi.da-06
> @fujitsu.com/
> [2]
> https://lore.kernel.org/linux-cxl/20240227083313.87699-1-kobayashi.da-06@
> fujitsu.com/
> [3]
> https://lore.kernel.org/linux-cxl/20240312080559.14904-1-kobayashi.da-06@
> fujitsu.com/
> [4]
> https://lore.kernel.org/linux-cxl/20240409073528.13214-1-kobayashi.da-06@
> fujitsu.com/
> [5]
> https://lore.kernel.org/linux-cxl/20240412070715.16160-1-kobayashi.da-06@
> fujitsu.com/
> [6]
> https://lore.kernel.org/linux-cxl/20240424050102.26788-1-kobayashi.da-06@
> fujitsu.com/
> [7]
> https://lore.kernel.org/linux-cxl/20240510073710.98953-1-kobayashi.da-06@
> fujitsu.com/
> [8]
> https://lore.kernel.org/linux-cxl/20240606074814.5633-1-kobayashi.da-06@f
> ujitsu.com/
> [9]
> https://lore.kernel.org/linux-cxl/20240610082222.22772-1-kobayashi.da-06@
> fujitsu.com/
> [10]
> https://lore.kernel.org/linux-cxl/20240611055254.61203-1-kobayashi.da-06@
> fujitsu.com/
> [11]
> https://lore.kernel.org/linux-cxl/20240612075940.92500-1-kobayashi.da-06@
> fujitsu.com/
> [12]
> https://lore.kernel.org/linux-cxl/20240614045611.58658-1-kobayashi.da-06@
> fujitsu.com/
> [13]
> https://lore.kernel.org/linux-cxl/20240617043702.62028-1-kobayashi.da-06@
> fujitsu.com/
> [14]
> https://lore.kernel.org/linux-cxl/20240618042941.96893-1-kobayashi.da-06@
> fujitsu.com/
> [15]
> https://lore.kernel.org/linux-cxl/20240716042540.89639-1-kobayashi.da-06@
> fujitsu.com/
> [16]
> https://lore.kernel.org/linux-cxl/20240815005510.220835-1-kobayashi.da-06
> @fujitsu.com/
> 
> Kobayashi,Daisuke (2):
>   cxl/core/regs: Add rcd_pcie_cap initialization
>   cxl/pci: Add sysfs attribute for CXL 1.1 device link status
> 
>  drivers/cxl/core/core.h |   5 ++
>  drivers/cxl/core/regs.c |  56 ++++++++++++++++++++
>  drivers/cxl/cxl.h       |   9 ++++
>  drivers/cxl/pci.c       | 110
> +++++++++++++++++++++++++++++++++++-----
>  4 files changed, 167 insertions(+), 13 deletions(-)
> 
> --
> 2.45.0

Re: [PATCH v17 0/2] Export cxl1.1 device link status register value to pci device sysfs.

[Dave Jiang]

On 9/24/24 12:36 AM, Daisuke Kobayashi (Fujitsu) wrote:
> Hi, Dan. Could you please review this patch?
> I think I've fixed the issues you mentioned.

Hi Daisuke,
In the mean time can you please respin and fix these two kbot issues?
https://lore.kernel.org/linux-cxl/202409040011.kaajNuCb-lkp@intel.com/
https://lore.kernel.org/linux-cxl/202409040010.afyGcWUe-lkp@intel.com/

> 
> Thank you.
> 
> Kobayashi Daisuke wrote:
>> Subject: [PATCH v17 0/2] Export cxl1.1 device link status register value to pci
>> device sysfs.
>>
>> CXL devices are extensions of PCIe. Therefore, from CXL2.0 onwards, the link
>> status can be output in the same way as traditional PCIe.
>> However, unlike devices from CXL2.0 onwards, CXL1.1 requires a different
>> method to obtain the link status from traditional PCIe.
>> This is because the link status of the CXL1.1 device is not mapped in the
>> configuration space (as per cxl3.0 specification 8.1).
>> Instead, the configuration space containing the link status is mapped to the
>> memory mapped register region (as per cxl3.0 specification 8.2, Table 8-18).
>> Therefore, the current lspci has a problem where it does not display the link
>> status of the CXL1.1 device.
>> Solve these issues with sysfs attributes to export the status registers hidden in
>> the RCRB.
>>
>> The procedure is as follows:
>> First, obtain the RCRB address within the cxl driver, then access the
>> configuration space. Next, output the link status information from the
>> configuration space to sysfs. Ultimately, the expectation is that this sysfs file
>> will be consumed by PCI user tools to utilize link status information.
>>
>> This patch series relies on the functions defined in the following patches.
>> https://lore.kernel.org/linux-cxl/20240830013138.2256244-1-ming4.li@intel.c
>> om/
>>
>> Changes
>> v1[1] -> v2:
>> - Modified to perform rcrb access within the CXL driver.
>> - Added new attributes to the sysfs of the PCI device.
>> - Output the link status information to the sysfs of the PCI device.
>> - Retrieve information from sysfs as the source when displaying information in
>> lspci.
>>
>> v2[2] -> v3:
>> - Fix unnecessary initialization and wrong types (Bjohn).
>> - Create a helper function for getting a PCIe capability offset (Bjohn).
>> - Move platform-specific implementation to the lib directory in pciutils
>> (Martin).
>>
>> v3[3] -> v4:
>> - RCRB register values are read once and cached.
>> - Added a new attribute to the sysfs of the PCI device.
>> - Separate lspci implementation from this patch.
>>
>> v4[4] -> v5:
>> - Use macros for bitwise operations
>> - Fix RCRB access to use cxl_memdev
>>
>> v5[5] -> v6:
>> - Add and use masks for RCRB register values
>>
>> v6[6] -> v7:
>> - Fix comments on white space inline
>>
>> v7[7] -> v8:
>> - Change the cache value to offset
>> - Access memory map area in rcd_*_show() functions
>>
>> v8[8] -> v9:
>> - Map the pcie cap in for all the time the driver is bound to the device.
>> - Add mapping the pcie cap in cxl_rcd_component_reg_phys().
>>
>> v9[9] -> v10:
>> - Change a utility function for getting PCIe capability.
>> - Fix tab alignment issue, error handling, and apply suggestions from Jonathan.
>>
>> v10[10] -> v11:
>> - Add functions to have one function do only one thing.
>> - Add a size parameter to utility function arguments and consolidated them into
>> one.
>>
>> v11[11] -> v12:
>> - Fix the error handling in cxl_pci_setup_regs().
>> - Fix and clean up some details.
>>
>> v12[12] -> v13:
>> - Fix and clean up some details.
>>
>> v13[13] -> v14:
>> - Fix and clean up some details.
>>
>> v14[14] -> v15:
>> - Change dport lookup to be done only once.
>> - Fix the visibility of cxl_rcrb_to_linkcap().
>>
>> v15[15] -> v16:
>> - Fix the port leak bug by introduce a new scope-based-free handler
>> - Improve the variable names.
>>
>> v16[16] -> v17:
>> - Change used function for making struct cxl_port *port
>>
>> [1]
>> https://lore.kernel.org/linux-cxl/20231220050738.178481-1-kobayashi.da-06
>> @fujitsu.com/
>> [2]
>> https://lore.kernel.org/linux-cxl/20240227083313.87699-1-kobayashi.da-06@
>> fujitsu.com/
>> [3]
>> https://lore.kernel.org/linux-cxl/20240312080559.14904-1-kobayashi.da-06@
>> fujitsu.com/
>> [4]
>> https://lore.kernel.org/linux-cxl/20240409073528.13214-1-kobayashi.da-06@
>> fujitsu.com/
>> [5]
>> https://lore.kernel.org/linux-cxl/20240412070715.16160-1-kobayashi.da-06@
>> fujitsu.com/
>> [6]
>> https://lore.kernel.org/linux-cxl/20240424050102.26788-1-kobayashi.da-06@
>> fujitsu.com/
>> [7]
>> https://lore.kernel.org/linux-cxl/20240510073710.98953-1-kobayashi.da-06@
>> fujitsu.com/
>> [8]
>> https://lore.kernel.org/linux-cxl/20240606074814.5633-1-kobayashi.da-06@f
>> ujitsu.com/
>> [9]
>> https://lore.kernel.org/linux-cxl/20240610082222.22772-1-kobayashi.da-06@
>> fujitsu.com/
>> [10]
>> https://lore.kernel.org/linux-cxl/20240611055254.61203-1-kobayashi.da-06@
>> fujitsu.com/
>> [11]
>> https://lore.kernel.org/linux-cxl/20240612075940.92500-1-kobayashi.da-06@
>> fujitsu.com/
>> [12]
>> https://lore.kernel.org/linux-cxl/20240614045611.58658-1-kobayashi.da-06@
>> fujitsu.com/
>> [13]
>> https://lore.kernel.org/linux-cxl/20240617043702.62028-1-kobayashi.da-06@
>> fujitsu.com/
>> [14]
>> https://lore.kernel.org/linux-cxl/20240618042941.96893-1-kobayashi.da-06@
>> fujitsu.com/
>> [15]
>> https://lore.kernel.org/linux-cxl/20240716042540.89639-1-kobayashi.da-06@
>> fujitsu.com/
>> [16]
>> https://lore.kernel.org/linux-cxl/20240815005510.220835-1-kobayashi.da-06
>> @fujitsu.com/
>>
>> Kobayashi,Daisuke (2):
>>   cxl/core/regs: Add rcd_pcie_cap initialization
>>   cxl/pci: Add sysfs attribute for CXL 1.1 device link status
>>
>>  drivers/cxl/core/core.h |   5 ++
>>  drivers/cxl/core/regs.c |  56 ++++++++++++++++++++
>>  drivers/cxl/cxl.h       |   9 ++++
>>  drivers/cxl/pci.c       | 110
>> +++++++++++++++++++++++++++++++++++-----
>>  4 files changed, 167 insertions(+), 13 deletions(-)
>>
>> --
>> 2.45.0
> 
> 

RE: [PATCH v17 0/2] Export cxl1.1 device link status register value to pci device sysfs.

[Daisuke Kobayashi (Fujitsu)]

Dave Jiang wrote:
> On 9/24/24 12:36 AM, Daisuke Kobayashi (Fujitsu) wrote:
> > Hi, Dan. Could you please review this patch?
> > I think I've fixed the issues you mentioned.
> 
> Hi Daisuke,
> In the mean time can you please respin and fix these two kbot issues?
> https://lore.kernel.org/linux-cxl/202409040011.kaajNuCb-lkp@intel.com/
> https://lore.kernel.org/linux-cxl/202409040010.afyGcWUe-lkp@intel.com/
> 
> >
> > Thank you.
> >
Thank you for your comment.

This patch was using a function that hasn't been merged yet, as per Dan's instructions. 
It seems that the patch containing that function has now been merged into the cxl-next branch.
https://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl.git/commit/?h=next&id=dd2617ebd2a69c012001a29274557199409eff39

I apologize for the lack of explanation and any confusion this may have caused.

While the situation may be different from when kbot reported the error, 
could you please advise what modifications are needed here?

> > Kobayashi Daisuke wrote:
> >> Subject: [PATCH v17 0/2] Export cxl1.1 device link status register
> >> value to pci device sysfs.
> >>
> >> CXL devices are extensions of PCIe. Therefore, from CXL2.0 onwards,
> >> the link status can be output in the same way as traditional PCIe.
> >> However, unlike devices from CXL2.0 onwards, CXL1.1 requires a
> >> different method to obtain the link status from traditional PCIe.
> >> This is because the link status of the CXL1.1 device is not mapped in
> >> the configuration space (as per cxl3.0 specification 8.1).
> >> Instead, the configuration space containing the link status is mapped
> >> to the memory mapped register region (as per cxl3.0 specification 8.2, Table
> 8-18).
> >> Therefore, the current lspci has a problem where it does not display
> >> the link status of the CXL1.1 device.
> >> Solve these issues with sysfs attributes to export the status
> >> registers hidden in the RCRB.
> >>
> >> The procedure is as follows:
> >> First, obtain the RCRB address within the cxl driver, then access the
> >> configuration space. Next, output the link status information from
> >> the configuration space to sysfs. Ultimately, the expectation is that
> >> this sysfs file will be consumed by PCI user tools to utilize link status
> information.
> >>
> >> This patch series relies on the functions defined in the following patches.
> >> https://lore.kernel.org/linux-cxl/20240830013138.2256244-1-ming4.li@i
> >> ntel.c
> >> om/
> >>
> >> Changes
> >> v1[1] -> v2:
> >> - Modified to perform rcrb access within the CXL driver.
> >> - Added new attributes to the sysfs of the PCI device.
> >> - Output the link status information to the sysfs of the PCI device.
> >> - Retrieve information from sysfs as the source when displaying
> >> information in lspci.
> >>
> >> v2[2] -> v3:
> >> - Fix unnecessary initialization and wrong types (Bjohn).
> >> - Create a helper function for getting a PCIe capability offset (Bjohn).
> >> - Move platform-specific implementation to the lib directory in
> >> pciutils (Martin).
> >>
> >> v3[3] -> v4:
> >> - RCRB register values are read once and cached.
> >> - Added a new attribute to the sysfs of the PCI device.
> >> - Separate lspci implementation from this patch.
> >>
> >> v4[4] -> v5:
> >> - Use macros for bitwise operations
> >> - Fix RCRB access to use cxl_memdev
> >>
> >> v5[5] -> v6:
> >> - Add and use masks for RCRB register values
> >>
> >> v6[6] -> v7:
> >> - Fix comments on white space inline
> >>
> >> v7[7] -> v8:
> >> - Change the cache value to offset
> >> - Access memory map area in rcd_*_show() functions
> >>
> >> v8[8] -> v9:
> >> - Map the pcie cap in for all the time the driver is bound to the device.
> >> - Add mapping the pcie cap in cxl_rcd_component_reg_phys().
> >>
> >> v9[9] -> v10:
> >> - Change a utility function for getting PCIe capability.
> >> - Fix tab alignment issue, error handling, and apply suggestions from
> Jonathan.
> >>
> >> v10[10] -> v11:
> >> - Add functions to have one function do only one thing.
> >> - Add a size parameter to utility function arguments and consolidated
> >> them into one.
> >>
> >> v11[11] -> v12:
> >> - Fix the error handling in cxl_pci_setup_regs().
> >> - Fix and clean up some details.
> >>
> >> v12[12] -> v13:
> >> - Fix and clean up some details.
> >>
> >> v13[13] -> v14:
> >> - Fix and clean up some details.
> >>
> >> v14[14] -> v15:
> >> - Change dport lookup to be done only once.
> >> - Fix the visibility of cxl_rcrb_to_linkcap().
> >>
> >> v15[15] -> v16:
> >> - Fix the port leak bug by introduce a new scope-based-free handler
> >> - Improve the variable names.
> >>
> >> v16[16] -> v17:
> >> - Change used function for making struct cxl_port *port
> >>
> >> [1]
> >> https://lore.kernel.org/linux-cxl/20231220050738.178481-1-kobayashi.d
> >> a-06
> >> @fujitsu.com/
> >> [2]
> >> https://lore.kernel.org/linux-cxl/20240227083313.87699-1-kobayashi.da
> >> -06@
> >> fujitsu.com/
> >> [3]
> >> https://lore.kernel.org/linux-cxl/20240312080559.14904-1-kobayashi.da
> >> -06@
> >> fujitsu.com/
> >> [4]
> >> https://lore.kernel.org/linux-cxl/20240409073528.13214-1-kobayashi.da
> >> -06@
> >> fujitsu.com/
> >> [5]
> >> https://lore.kernel.org/linux-cxl/20240412070715.16160-1-kobayashi.da
> >> -06@
> >> fujitsu.com/
> >> [6]
> >> https://lore.kernel.org/linux-cxl/20240424050102.26788-1-kobayashi.da
> >> -06@
> >> fujitsu.com/
> >> [7]
> >> https://lore.kernel.org/linux-cxl/20240510073710.98953-1-kobayashi.da
> >> -06@
> >> fujitsu.com/
> >> [8]
> >> https://lore.kernel.org/linux-cxl/20240606074814.5633-1-kobayashi.da-
> >> 06@f
> >> ujitsu.com/
> >> [9]
> >> https://lore.kernel.org/linux-cxl/20240610082222.22772-1-kobayashi.da
> >> -06@
> >> fujitsu.com/
> >> [10]
> >> https://lore.kernel.org/linux-cxl/20240611055254.61203-1-kobayashi.da
> >> -06@
> >> fujitsu.com/
> >> [11]
> >> https://lore.kernel.org/linux-cxl/20240612075940.92500-1-kobayashi.da
> >> -06@
> >> fujitsu.com/
> >> [12]
> >> https://lore.kernel.org/linux-cxl/20240614045611.58658-1-kobayashi.da
> >> -06@
> >> fujitsu.com/
> >> [13]
> >> https://lore.kernel.org/linux-cxl/20240617043702.62028-1-kobayashi.da
> >> -06@
> >> fujitsu.com/
> >> [14]
> >> https://lore.kernel.org/linux-cxl/20240618042941.96893-1-kobayashi.da
> >> -06@
> >> fujitsu.com/
> >> [15]
> >> https://lore.kernel.org/linux-cxl/20240716042540.89639-1-kobayashi.da
> >> -06@
> >> fujitsu.com/
> >> [16]
> >> https://lore.kernel.org/linux-cxl/20240815005510.220835-1-kobayashi.d
> >> a-06
> >> @fujitsu.com/
> >>
> >> Kobayashi,Daisuke (2):
> >>   cxl/core/regs: Add rcd_pcie_cap initialization
> >>   cxl/pci: Add sysfs attribute for CXL 1.1 device link status
> >>
> >>  drivers/cxl/core/core.h |   5 ++
> >>  drivers/cxl/core/regs.c |  56 ++++++++++++++++++++
> >>  drivers/cxl/cxl.h       |   9 ++++
> >>  drivers/cxl/pci.c       | 110
> >> +++++++++++++++++++++++++++++++++++-----
> >>  4 files changed, 167 insertions(+), 13 deletions(-)
> >>
> >> --
> >> 2.45.0
> >
> >

Re: [PATCH v17 0/2] Export cxl1.1 device link status register value to pci device sysfs.

[Dave Jiang]

On 9/24/24 5:20 PM, Daisuke Kobayashi (Fujitsu) wrote:
> Dave Jiang wrote:
>> On 9/24/24 12:36 AM, Daisuke Kobayashi (Fujitsu) wrote:
>>> Hi, Dan. Could you please review this patch?
>>> I think I've fixed the issues you mentioned.
>>
>> Hi Daisuke,
>> In the mean time can you please respin and fix these two kbot issues?
>> https://lore.kernel.org/linux-cxl/202409040011.kaajNuCb-lkp@intel.com/
>> https://lore.kernel.org/linux-cxl/202409040010.afyGcWUe-lkp@intel.com/
>>
>>>
>>> Thank you.
>>>
> Thank you for your comment.
> 
> This patch was using a function that hasn't been merged yet, as per Dan's instructions. 
> It seems that the patch containing that function has now been merged into the cxl-next branch.
> https://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl.git/commit/?h=next&id=dd2617ebd2a69c012001a29274557199409eff39
> 
> I apologize for the lack of explanation and any confusion this may have caused.
> 
> While the situation may be different from when kbot reported the error, 
> could you please advise what modifications are needed here?

The series has missed the 6.12 merge window unfortunately. My suggestion is to post v18 rebased against 6.12-rc1 (given that the patch you need should be upstream by then) and the kbot issues hopefully should clear up. Hopefully Dan will get a chance to review the changes in the next cycle and let's get this into the 6.13 merge window.

> 
>>> Kobayashi Daisuke wrote:
>>>> Subject: [PATCH v17 0/2] Export cxl1.1 device link status register
>>>> value to pci device sysfs.
>>>>
>>>> CXL devices are extensions of PCIe. Therefore, from CXL2.0 onwards,
>>>> the link status can be output in the same way as traditional PCIe.
>>>> However, unlike devices from CXL2.0 onwards, CXL1.1 requires a
>>>> different method to obtain the link status from traditional PCIe.
>>>> This is because the link status of the CXL1.1 device is not mapped in
>>>> the configuration space (as per cxl3.0 specification 8.1).
>>>> Instead, the configuration space containing the link status is mapped
>>>> to the memory mapped register region (as per cxl3.0 specification 8.2, Table
>> 8-18).
>>>> Therefore, the current lspci has a problem where it does not display
>>>> the link status of the CXL1.1 device.
>>>> Solve these issues with sysfs attributes to export the status
>>>> registers hidden in the RCRB.
>>>>
>>>> The procedure is as follows:
>>>> First, obtain the RCRB address within the cxl driver, then access the
>>>> configuration space. Next, output the link status information from
>>>> the configuration space to sysfs. Ultimately, the expectation is that
>>>> this sysfs file will be consumed by PCI user tools to utilize link status
>> information.
>>>>
>>>> This patch series relies on the functions defined in the following patches.
>>>> https://lore.kernel.org/linux-cxl/20240830013138.2256244-1-ming4.li@i
>>>> ntel.c
>>>> om/
>>>>
>>>> Changes
>>>> v1[1] -> v2:
>>>> - Modified to perform rcrb access within the CXL driver.
>>>> - Added new attributes to the sysfs of the PCI device.
>>>> - Output the link status information to the sysfs of the PCI device.
>>>> - Retrieve information from sysfs as the source when displaying
>>>> information in lspci.
>>>>
>>>> v2[2] -> v3:
>>>> - Fix unnecessary initialization and wrong types (Bjohn).
>>>> - Create a helper function for getting a PCIe capability offset (Bjohn).
>>>> - Move platform-specific implementation to the lib directory in
>>>> pciutils (Martin).
>>>>
>>>> v3[3] -> v4:
>>>> - RCRB register values are read once and cached.
>>>> - Added a new attribute to the sysfs of the PCI device.
>>>> - Separate lspci implementation from this patch.
>>>>
>>>> v4[4] -> v5:
>>>> - Use macros for bitwise operations
>>>> - Fix RCRB access to use cxl_memdev
>>>>
>>>> v5[5] -> v6:
>>>> - Add and use masks for RCRB register values
>>>>
>>>> v6[6] -> v7:
>>>> - Fix comments on white space inline
>>>>
>>>> v7[7] -> v8:
>>>> - Change the cache value to offset
>>>> - Access memory map area in rcd_*_show() functions
>>>>
>>>> v8[8] -> v9:
>>>> - Map the pcie cap in for all the time the driver is bound to the device.
>>>> - Add mapping the pcie cap in cxl_rcd_component_reg_phys().
>>>>
>>>> v9[9] -> v10:
>>>> - Change a utility function for getting PCIe capability.
>>>> - Fix tab alignment issue, error handling, and apply suggestions from
>> Jonathan.
>>>>
>>>> v10[10] -> v11:
>>>> - Add functions to have one function do only one thing.
>>>> - Add a size parameter to utility function arguments and consolidated
>>>> them into one.
>>>>
>>>> v11[11] -> v12:
>>>> - Fix the error handling in cxl_pci_setup_regs().
>>>> - Fix and clean up some details.
>>>>
>>>> v12[12] -> v13:
>>>> - Fix and clean up some details.
>>>>
>>>> v13[13] -> v14:
>>>> - Fix and clean up some details.
>>>>
>>>> v14[14] -> v15:
>>>> - Change dport lookup to be done only once.
>>>> - Fix the visibility of cxl_rcrb_to_linkcap().
>>>>
>>>> v15[15] -> v16:
>>>> - Fix the port leak bug by introduce a new scope-based-free handler
>>>> - Improve the variable names.
>>>>
>>>> v16[16] -> v17:
>>>> - Change used function for making struct cxl_port *port
>>>>
>>>> [1]
>>>> https://lore.kernel.org/linux-cxl/20231220050738.178481-1-kobayashi.d
>>>> a-06
>>>> @fujitsu.com/
>>>> [2]
>>>> https://lore.kernel.org/linux-cxl/20240227083313.87699-1-kobayashi.da
>>>> -06@
>>>> fujitsu.com/
>>>> [3]
>>>> https://lore.kernel.org/linux-cxl/20240312080559.14904-1-kobayashi.da
>>>> -06@
>>>> fujitsu.com/
>>>> [4]
>>>> https://lore.kernel.org/linux-cxl/20240409073528.13214-1-kobayashi.da
>>>> -06@
>>>> fujitsu.com/
>>>> [5]
>>>> https://lore.kernel.org/linux-cxl/20240412070715.16160-1-kobayashi.da
>>>> -06@
>>>> fujitsu.com/
>>>> [6]
>>>> https://lore.kernel.org/linux-cxl/20240424050102.26788-1-kobayashi.da
>>>> -06@
>>>> fujitsu.com/
>>>> [7]
>>>> https://lore.kernel.org/linux-cxl/20240510073710.98953-1-kobayashi.da
>>>> -06@
>>>> fujitsu.com/
>>>> [8]
>>>> https://lore.kernel.org/linux-cxl/20240606074814.5633-1-kobayashi.da-
>>>> 06@f
>>>> ujitsu.com/
>>>> [9]
>>>> https://lore.kernel.org/linux-cxl/20240610082222.22772-1-kobayashi.da
>>>> -06@
>>>> fujitsu.com/
>>>> [10]
>>>> https://lore.kernel.org/linux-cxl/20240611055254.61203-1-kobayashi.da
>>>> -06@
>>>> fujitsu.com/
>>>> [11]
>>>> https://lore.kernel.org/linux-cxl/20240612075940.92500-1-kobayashi.da
>>>> -06@
>>>> fujitsu.com/
>>>> [12]
>>>> https://lore.kernel.org/linux-cxl/20240614045611.58658-1-kobayashi.da
>>>> -06@
>>>> fujitsu.com/
>>>> [13]
>>>> https://lore.kernel.org/linux-cxl/20240617043702.62028-1-kobayashi.da
>>>> -06@
>>>> fujitsu.com/
>>>> [14]
>>>> https://lore.kernel.org/linux-cxl/20240618042941.96893-1-kobayashi.da
>>>> -06@
>>>> fujitsu.com/
>>>> [15]
>>>> https://lore.kernel.org/linux-cxl/20240716042540.89639-1-kobayashi.da
>>>> -06@
>>>> fujitsu.com/
>>>> [16]
>>>> https://lore.kernel.org/linux-cxl/20240815005510.220835-1-kobayashi.d
>>>> a-06
>>>> @fujitsu.com/
>>>>
>>>> Kobayashi,Daisuke (2):
>>>>   cxl/core/regs: Add rcd_pcie_cap initialization
>>>>   cxl/pci: Add sysfs attribute for CXL 1.1 device link status
>>>>
>>>>  drivers/cxl/core/core.h |   5 ++
>>>>  drivers/cxl/core/regs.c |  56 ++++++++++++++++++++
>>>>  drivers/cxl/cxl.h       |   9 ++++
>>>>  drivers/cxl/pci.c       | 110
>>>> +++++++++++++++++++++++++++++++++++-----
>>>>  4 files changed, 167 insertions(+), 13 deletions(-)
>>>>
>>>> --
>>>> 2.45.0
>>>
>>>
>