From: <shiju.jose@huawei.com>
To: <dave.jiang@intel.com>, <dan.j.williams@intel.com>,
<jonathan.cameron@huawei.com>, <alison.schofield@intel.com>,
<nifan.cxl@gmail.com>, <vishal.l.verma@intel.com>,
<ira.weiny@intel.com>, <dave@stgolabs.net>,
<linux-cxl@vger.kernel.org>
Cc: <linux-kernel@vger.kernel.org>, <linuxarm@huawei.com>,
<tanxiaofei@huawei.com>, <prime.zeng@hisilicon.com>,
<shiju.jose@huawei.com>
Subject: [PATCH v4 2/6] cxl/events: Add Component Identifier formatting for CXL spec rev 3.1
Date: Wed, 20 Nov 2024 09:37:41 +0000 [thread overview]
Message-ID: <20241120093745.1847-3-shiju.jose@huawei.com> (raw)
In-Reply-To: <20241120093745.1847-1-shiju.jose@huawei.com>
From: Shiju Jose <shiju.jose@huawei.com>
Add Component Identifier formatting for CXL spec rev 3.1, Section
8.2.9.2.1, Table 8-44.
Examples for Component Identifier format in trace log,
validity_flags='CHANNEL|RANK|DEVICE|COMPONENT|COMPONENT PLDM FORMAT' \
comp_id=03 74 c5 08 9a 1a 0b fc d2 7e 2f 31 9b 3c 81 4d \
comp_id_pldm_valid_flags='PLDM Entity ID | Resource ID' \
pldm_entity_id=74 c5 08 9a 1a 0b pldm_resource_id=fc d2 7e 2f \
validity_flags='COMPONENT|COMPONENT PLDM FORMAT' \
comp_id=02 74 c5 08 9a 1a 0b fc d2 7e 2f 31 9b 3c 81 4d \
comp_id_pldm_valid_flags='Resource ID' \
pldm_entity_id=0x00 pldm_resource_id=fc d2 7e 2f
If the validity flags for component ID/component ID format or PLDM ID or
resource ID are not set, then pldm_entity_id=0x00 or pldm_resource_id=0x00
would be printed.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
---
drivers/cxl/core/trace.h | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h
index 7305974e2301..8e9d80e34a28 100644
--- a/drivers/cxl/core/trace.h
+++ b/drivers/cxl/core/trace.h
@@ -268,6 +268,23 @@ TRACE_EVENT(cxl_generic_event,
{ CXL_DPA_NOT_REPAIRABLE, "NOT_REPAIRABLE" } \
)
+/*
+ * Component ID Format
+ * CXL 3.1 section 8.2.9.2.1; Table 8-44
+ */
+#define CXL_PLDM_COMPONENT_ID_ENTITY_VALID BIT(0)
+#define CXL_PLDM_COMPONENT_ID_RES_VALID BIT(1)
+
+#define show_pldm_entity_id(flags, valid_comp_id, valid_id_format, comp_id) \
+ (flags & valid_comp_id && flags & valid_id_format) ? \
+ (comp_id[0] & CXL_PLDM_COMPONENT_ID_ENTITY_VALID) ? \
+ __print_hex(&comp_id[1], 6) : "0x00" : "0x00"
+
+#define show_pldm_resource_id(flags, valid_comp_id, valid_id_format, comp_id) \
+ (flags & valid_comp_id && flags & valid_id_format) ? \
+ (comp_id[0] & CXL_PLDM_COMPONENT_ID_RES_VALID) ? \
+ __print_hex(&comp_id[7], 4) : "0x00" : "0x00"
+
/*
* General Media Event Record - GMER
* CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43
--
2.43.0
next prev parent reply other threads:[~2024-11-20 9:38 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-20 9:37 [PATCH v4 0/6] Update Event Records to CXL spec rev 3.1 shiju.jose
2024-11-20 9:37 ` [PATCH v4 1/6] cxl/events: Update Common Event Record " shiju.jose
2024-11-26 17:27 ` Fan Ni
2024-11-27 10:15 ` Shiju Jose
2024-11-20 9:37 ` shiju.jose [this message]
2024-11-20 9:37 ` [PATCH v4 3/6] cxl/events: Update General Media " shiju.jose
2024-11-26 11:51 ` Shiju Jose
2024-11-26 17:02 ` Steven Rostedt
2024-11-27 10:12 ` Shiju Jose
2024-11-27 15:41 ` Steven Rostedt
2024-11-27 18:20 ` Shiju Jose
2024-11-27 18:34 ` Steven Rostedt
2024-11-28 10:01 ` Shiju Jose
2024-11-29 13:22 ` Shiju Jose
2024-12-03 15:21 ` Shiju Jose
2024-12-04 11:35 ` Shiju Jose
2024-11-20 9:37 ` [PATCH v4 4/6] cxl/events: Update DRAM " shiju.jose
2024-11-20 9:37 ` [PATCH v4 5/6] cxl/events: Update Memory Module " shiju.jose
2024-11-20 9:37 ` [PATCH v4 6/6] cxl/test: Update test code for event records " shiju.jose
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