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From: Robert Richter <rrichter@amd.com>
To: Alison Schofield <alison.schofield@intel.com>,
	Vishal Verma <vishal.l.verma@intel.com>,
	Ira Weiny <ira.weiny@intel.com>,
	Dan Williams <dan.j.williams@intel.com>,
	Jonathan Cameron <jonathan.cameron@huawei.com>,
	Dave Jiang <dave.jiang@intel.com>,
	Davidlohr Bueso <dave@stgolabs.net>
Cc: <linux-cxl@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	Gregory Price <gourry@gourry.net>,
	"Fabio M. De Francesco" <fabio.m.de.francesco@linux.intel.com>,
	Terry Bowman <terry.bowman@amd.com>,
	Robert Richter <rrichter@amd.com>
Subject: [PATCH v1 16/29] cxl/region: Use translated HPA ranges to calculate the endpoint position
Date: Tue, 7 Jan 2025 15:10:02 +0100	[thread overview]
Message-ID: <20250107141015.3367194-17-rrichter@amd.com> (raw)
In-Reply-To: <20250107141015.3367194-1-rrichter@amd.com>

To enable address translation, the calculation of the endpoint
position must use translated HPA ranges. The function
cxl_endpoint_initialize() already uses translation which could be
reused to calculate the endpoint position.

Use translated HPA address ranges for the calculation of endpoint
position by moving it to cxl_endpoint_initialize(). Create a function
cxl_port_calc_pos() for use in the iterator there, but keep a
simplified version of cxl_calc_interleave_pos() for the
non-auto-discovery code path without address translation since it is
not support there.

Signed-off-by: Robert Richter <rrichter@amd.com>
---
 drivers/cxl/core/region.c | 66 ++++++++++++++++++++++++++-------------
 1 file changed, 44 insertions(+), 22 deletions(-)

diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
index 007a2016760d..c1e384e80d10 100644
--- a/drivers/cxl/core/region.c
+++ b/drivers/cxl/core/region.c
@@ -1813,26 +1813,29 @@ static int find_pos_and_ways(struct cxl_port *port, struct range *range,
 }
 
 /**
- * cxl_calc_interleave_pos() - calculate an endpoint position in a region
- * @cxled: endpoint decoder member of given region
+ * cxl_port_calc_pos() - calculate an endpoint position for @port
+ * @port: Port the new position is calculated for.
+ * @range: The HPA address range for the port.
+ * @pos: Current position in the topology.
  *
- * The endpoint position is calculated by traversing the topology from
- * the endpoint to the root decoder and iteratively applying this
- * calculation:
+ * The endpoint position for the next port is calculated by applying
+ * this calculation:
  *
  *    position = position * parent_ways + parent_pos;
  *
  * ...where @position is inferred from switch and root decoder target lists.
  *
+ * The endpoint position of region can be calculated by traversing the
+ * topology from the endpoint to the root decoder and iteratively
+ * applying the function for each port.
+ *
  * Return: position >= 0 on success
  *	   -ENXIO on failure
  */
-static int cxl_calc_interleave_pos(struct cxl_endpoint_decoder *cxled)
+static int cxl_port_calc_pos(struct cxl_port *port, struct range *range,
+			     int pos)
 {
-	struct cxl_port *iter, *port = cxled_to_port(cxled);
-	struct cxl_memdev *cxlmd = cxled_to_memdev(cxled);
-	struct range *range = &cxled->cxld.hpa_range;
-	int parent_ways = 0, parent_pos = 0, pos = 0;
+	int parent_ways = 0, parent_pos = 0;
 	int rc;
 
 	/*
@@ -1864,17 +1867,30 @@ static int cxl_calc_interleave_pos(struct cxl_endpoint_decoder *cxled)
 	 * complex topologies, including those with switches.
 	 */
 
-	/* Iterate from endpoint to root_port refining the position */
-	for (iter = port; iter; iter = parent_port_of(iter)) {
-		if (is_cxl_root(iter))
-			break;
+	if (is_cxl_root(port))
+		return pos;
 
-		rc = find_pos_and_ways(iter, range, &parent_pos, &parent_ways);
-		if (rc)
-			return rc;
+	rc = find_pos_and_ways(port, range, &parent_pos, &parent_ways);
+	if (rc)
+		return rc;
 
-		pos = pos * parent_ways + parent_pos;
-	}
+	return pos * parent_ways + parent_pos;
+}
+
+static int cxl_calc_interleave_pos(struct cxl_endpoint_decoder *cxled)
+{
+	struct cxl_port *iter, *port = cxled_to_port(cxled);
+	struct cxl_memdev *cxlmd = cxled_to_memdev(cxled);
+	struct range *range = &cxled->cxld.hpa_range;
+	int pos = 0;
+
+	/*
+	 * Address translation is only supported for auto-discovery of
+	 * decoders. There is no need to support address translation
+	 * here.
+	 */
+	for (iter = cxled_to_port(cxled); iter; iter = parent_port_of(iter))
+		pos = cxl_port_calc_pos(iter, range, pos);
 
 	dev_dbg(&cxlmd->dev,
 		"decoder:%s parent:%s port:%s range:%#llx-%#llx pos:%d\n",
@@ -1892,7 +1908,6 @@ static int cxl_region_sort_targets(struct cxl_region *cxlr)
 	for (i = 0; i < p->nr_targets; i++) {
 		struct cxl_endpoint_decoder *cxled = p->targets[i];
 
-		cxled->pos = cxl_calc_interleave_pos(cxled);
 		/*
 		 * Record that sorting failed, but still continue to calc
 		 * cxled->pos so that follow-on code paths can reliably
@@ -3252,6 +3267,7 @@ static int cxl_endpoint_initialize(struct cxl_endpoint_decoder *cxled)
 	struct cxl_port *parent, *iter = cxled_to_port(cxled);
 	struct range hpa = cxled->cxld.hpa_range;
 	struct cxl_decoder *cxld = &cxled->cxld;
+	int pos = 0;
 
 	if (!iter || is_cxl_root(iter))
 		return -ENXIO;
@@ -3280,16 +3296,22 @@ static int cxl_endpoint_initialize(struct cxl_endpoint_decoder *cxled)
 		if (cxl_port_calc_hpa(parent, cxld, &hpa))
 			return -ENXIO;
 
+		/* Iterate from endpoint to root_port refining the position */
+		pos = cxl_port_calc_pos(iter, &hpa, pos);
+		if (pos < 0)
+			return pos;
+
 		iter = parent;
 	}
 
 	dev_dbg(cxld->dev.parent,
-		"%s:%s: range:%#llx-%#llx\n",
+		"%s:%s: range:%#llx-%#llx pos:%d\n",
 		dev_name(&cxled->cxld.dev), dev_name(&cxld->dev),
-		hpa.start, hpa.end);
+		hpa.start, hpa.end, pos);
 
 	cxled->cxlrd = to_cxl_root_decoder(&cxld->dev);
 	cxled->spa_range = hpa;
+	cxled->pos = pos;
 
 	return 0;
 }
-- 
2.39.5


  parent reply	other threads:[~2025-01-07 14:11 UTC|newest]

Thread overview: 117+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-07 14:09 [PATCH v1 00/29] cxl: Add address translation support and enable AMD Zen5 platforms Robert Richter
2025-01-07 14:09 ` [PATCH v1 01/29] cxl: Remove else after return Robert Richter
2025-01-07 16:10   ` Gregory Price
2025-01-07 16:37   ` Dave Jiang
2025-01-09 12:00     ` Robert Richter
2025-01-07 14:09 ` [PATCH v1 02/29] cxl/pci: Moving code in cxl_hdm_decode_init() Robert Richter
2025-01-07 16:18   ` Gregory Price
2025-01-29 12:47     ` Robert Richter
2025-01-07 14:09 ` [PATCH v1 03/29] cxl/pci: cxl_hdm_decode_init: Move comment Robert Richter
2025-01-07 16:46   ` Gregory Price
2025-01-07 14:09 ` [PATCH v1 04/29] cxl/pci: Add comments to cxl_hdm_decode_init() Robert Richter
2025-01-07 16:51   ` Gregory Price
2025-01-13 16:47     ` Jonathan Cameron
2025-01-07 14:09 ` [PATCH v1 05/29] cxl/region: Move find_cxl_root() to cxl_add_to_region() Robert Richter
2025-01-07 16:49   ` Gregory Price
2025-01-13 16:52   ` Jonathan Cameron
2025-01-07 14:09 ` [PATCH v1 06/29] cxl/region: Factor out code to find the root decoder Robert Richter
2025-01-07 16:57   ` Gregory Price
2025-01-13 16:59   ` Jonathan Cameron
2025-01-29 13:13     ` Robert Richter
2025-01-07 14:09 ` [PATCH v1 07/29] cxl/region: Factor out code to find a root decoder's region Robert Richter
2025-01-07 16:59   ` Gregory Price
2025-01-30 16:43     ` Robert Richter
2025-01-07 14:09 ` [PATCH v1 08/29] cxl/region: Split region registration into an initialization and adding part Robert Richter
2025-01-07 18:29   ` Gregory Price
2025-01-30 16:53     ` Robert Richter
2025-01-09  1:08   ` Li Ming
2025-01-09 10:30     ` Robert Richter
2025-01-07 14:09 ` [PATCH v1 09/29] cxl/region: Use iterator to find the root port in cxl_find_root_decoder() Robert Richter
2025-01-07 17:23   ` Gregory Price
2025-01-13 18:11   ` Jonathan Cameron
2025-01-07 14:09 ` [PATCH v1 10/29] cxl/region: Add function to find a port's switch decoder by range Robert Richter
2025-01-07 18:38   ` Gregory Price
2025-01-30 16:58     ` Robert Richter
2025-01-17 21:31   ` Ben Cheatham
2025-01-30 17:02     ` Robert Richter
2025-01-07 14:09 ` [PATCH v1 11/29] cxl/region: Unfold cxl_find_root_decoder() into cxl_endpoint_initialize() Robert Richter
2025-01-07 18:41   ` Gregory Price
2025-01-07 14:09 ` [PATCH v1 12/29] cxl: Modify address translation callback for generic use Robert Richter
2025-01-07 18:44   ` Gregory Price
2025-01-31 14:19     ` Robert Richter
2025-01-17 21:31   ` Ben Cheatham
2025-01-31 14:27     ` Robert Richter
2025-01-07 14:09 ` [PATCH v1 13/29] cxl: Introduce callback to translate an HPA range from a port to its parent Robert Richter
2025-01-07 18:47   ` Gregory Price
2025-01-07 14:10 ` [PATCH v1 14/29] cxl: Introduce parent_port_of() helper Robert Richter
2025-01-07 18:50   ` Gregory Price
2025-01-13 18:20     ` Jonathan Cameron
2025-01-07 14:10 ` [PATCH v1 15/29] cxl/region: Use an endpoint's SPA range to find a region Robert Richter
2025-01-07 19:14   ` Gregory Price
2025-02-05  8:48     ` Robert Richter
2025-01-14 10:59   ` Jonathan Cameron
2025-01-31 15:46     ` Robert Richter
2025-01-17 21:31   ` Ben Cheatham
2025-02-05  9:00     ` Robert Richter
2025-01-07 14:10 ` Robert Richter [this message]
2025-01-07 22:01   ` [PATCH v1 16/29] cxl/region: Use translated HPA ranges to calculate the endpoint position Gregory Price
2025-02-05 10:38     ` Robert Richter
2025-01-17 21:31   ` Ben Cheatham
2025-02-05 10:43     ` Robert Richter
2025-01-07 14:10 ` [PATCH v1 17/29] cxl/region: Rename function to cxl_find_decoder_early() Robert Richter
2025-01-07 22:06   ` Gregory Price
2025-02-05 10:56     ` Robert Richter
2025-01-07 14:10 ` [PATCH v1 18/29] cxl/region: Avoid duplicate call of cxl_find_decoder_early() Robert Richter
2025-01-07 22:11   ` Gregory Price
2025-01-07 14:10 ` [PATCH v1 19/29] cxl/region: Use endpoint's HPA range to find the port's decoder Robert Richter
2025-01-07 22:18   ` Gregory Price
2025-02-06 10:50     ` Robert Richter
2025-01-17 21:31   ` Ben Cheatham
2025-02-06 11:03     ` Robert Richter
2025-01-07 14:10 ` [PATCH v1 20/29] cxl/region: Use translated HPA ranges " Robert Richter
2025-01-07 22:33   ` Gregory Price
2025-02-06 11:31     ` Robert Richter
2025-01-07 14:10 ` [PATCH v1 21/29] cxl/region: Lock decoders that need address translation Robert Richter
2025-01-07 22:35   ` Gregory Price
2025-02-06 13:23     ` Robert Richter
2025-01-07 14:10 ` [PATCH v1 22/29] cxl/region: Use translated HPA ranges to create a region Robert Richter
2025-01-07 23:08   ` Gregory Price
2025-02-06 13:25     ` Robert Richter
2025-01-07 14:10 ` [PATCH v1 23/29] cxl/region: Use root decoders interleaving parameters " Robert Richter
2025-01-13 17:48   ` Alison Schofield
2025-02-14 13:06     ` Robert Richter
2025-01-07 14:10 ` [PATCH v1 24/29] cxl/region: Use endpoint's SPA range to check " Robert Richter
2025-01-13 17:38   ` Alison Schofield
2025-02-14 13:09     ` Robert Richter
2025-01-07 14:10 ` [PATCH v1 25/29] cxl/amd: Enable Zen5 address translation using ACPI PRMT Robert Richter
2025-01-07 16:32   ` Robert Richter
2025-01-07 23:28   ` Gregory Price
2025-01-08 14:52     ` Robert Richter
2025-01-08 15:49       ` Gregory Price
2025-01-08 15:48   ` Gregory Price
2025-01-09 10:14     ` Robert Richter
2025-01-14 11:13       ` Jonathan Cameron
2025-01-17  7:59         ` Robert Richter
2025-01-17 11:46           ` Jonathan Cameron
2025-01-17 14:10             ` Robert Richter
2025-01-09 22:25   ` Gregory Price
2025-01-15 15:05     ` Robert Richter
2025-01-15 17:05       ` Gregory Price
2025-01-15 22:24       ` Gregory Price
2025-01-17 14:06         ` Robert Richter
2025-01-10 22:48   ` Gregory Price
2025-01-17  8:41     ` Robert Richter
2025-01-17 21:32   ` Ben Cheatham
2025-01-28  9:29     ` Robert Richter
2025-01-07 14:10 ` [PATCH v1 26/29] MAINTAINERS: CXL: Add entry for AMD platform support (CXL_AMD) Robert Richter
2025-01-07 14:10 ` [PATCH v1 27/29] cxl/region: Show message on registration failure Robert Richter
2025-01-07 23:11   ` Gregory Price
2025-01-07 14:10 ` [PATCH v1 28/29] cxl/region: Show message on broken target list Robert Richter
2025-01-07 23:12   ` Gregory Price
2025-01-14 11:16   ` Jonathan Cameron
2025-02-06 21:23     ` Robert Richter
2025-02-07 17:51       ` Jonathan Cameron
2025-02-12  9:08         ` Robert Richter
2025-01-07 14:10 ` [PATCH v1 29/29] cxl: Show message when a decoder was added to a port Robert Richter
2025-01-07 23:15   ` Gregory Price
2025-01-13 18:41 ` [PATCH v1 00/29] cxl: Add address translation support and enable AMD Zen5 platforms Alison Schofield

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