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From: Robert Richter <rrichter@amd.com>
To: Alison Schofield <alison.schofield@intel.com>,
	Vishal Verma <vishal.l.verma@intel.com>,
	Ira Weiny <ira.weiny@intel.com>,
	Dan Williams <dan.j.williams@intel.com>,
	Jonathan Cameron <Jonathan.Cameron@huawei.com>,
	Dave Jiang <dave.jiang@intel.com>,
	Davidlohr Bueso <dave@stgolabs.net>
Cc: <linux-cxl@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	Gregory Price <gourry@gourry.net>,
	"Fabio M. De Francesco" <fabio.m.de.francesco@linux.intel.com>,
	Terry Bowman <terry.bowman@amd.com>,
	Robert Richter <rrichter@amd.com>
Subject: [PATCH v2 13/15] cxl/x86: Prepare for architectural platform setup
Date: Tue, 18 Feb 2025 14:23:54 +0100	[thread overview]
Message-ID: <20250218132356.1809075-14-rrichter@amd.com> (raw)
In-Reply-To: <20250218132356.1809075-1-rrichter@amd.com>

In preparation of an architectural, vendor and platform specific port
setup, add a function arch_cxl_port_platform_setup() that can be used
to handle and implement architecture and platform specific code.

Signed-off-by: Robert Richter <rrichter@amd.com>
---
 drivers/cxl/core/Makefile     |  2 ++
 drivers/cxl/core/core.h       |  1 +
 drivers/cxl/core/port.c       |  4 ++++
 drivers/cxl/core/x86/common.c | 12 ++++++++++++
 4 files changed, 19 insertions(+)
 create mode 100644 drivers/cxl/core/x86/common.c

diff --git a/drivers/cxl/core/Makefile b/drivers/cxl/core/Makefile
index 9259bcc6773c..db1d16d39037 100644
--- a/drivers/cxl/core/Makefile
+++ b/drivers/cxl/core/Makefile
@@ -16,3 +16,5 @@ cxl_core-y += pmu.o
 cxl_core-y += cdat.o
 cxl_core-$(CONFIG_TRACING) += trace.o
 cxl_core-$(CONFIG_CXL_REGION) += region.o
+
+cxl_core-$(CONFIG_X86)		+= x86/common.o
diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h
index a20ea2b7d1a4..e2955f91fd98 100644
--- a/drivers/cxl/core/core.h
+++ b/drivers/cxl/core/core.h
@@ -118,5 +118,6 @@ int cxl_port_get_switch_dport_bandwidth(struct cxl_port *port,
 					struct access_coordinate *c);
 
 int cxl_gpf_port_setup(struct device *dport_dev, struct cxl_port *port);
+void arch_cxl_port_platform_setup(struct cxl_port *port);
 
 #endif /* __CXL_CORE_H__ */
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index d19930c009ce..e94671ea8455 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -841,6 +841,8 @@ static void cxl_debugfs_create_dport_dir(struct cxl_dport *dport)
 			    &cxl_einj_inject_fops);
 }
 
+void __weak arch_cxl_port_platform_setup(struct cxl_port *port) { }
+
 static int cxl_port_add(struct cxl_port *port,
 			resource_size_t component_reg_phys,
 			struct cxl_dport *parent_dport)
@@ -878,6 +880,8 @@ static int cxl_port_add(struct cxl_port *port,
 			return rc;
 	}
 
+	arch_cxl_port_platform_setup(port);
+
 	rc = device_add(dev);
 	if (rc)
 		return rc;
diff --git a/drivers/cxl/core/x86/common.c b/drivers/cxl/core/x86/common.c
new file mode 100644
index 000000000000..eeb9bdadb26d
--- /dev/null
+++ b/drivers/cxl/core/x86/common.c
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2025 Advanced Micro Devices, Inc.
+ */
+
+#include <cxl.h>
+
+#include "../core.h"
+
+void arch_cxl_port_platform_setup(struct cxl_port *port)
+{
+}
-- 
2.39.5


  parent reply	other threads:[~2025-02-18 13:25 UTC|newest]

Thread overview: 61+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-18 13:23 [PATCH v2 00/15] cxl: Address translation support, part 2: Generic support and AMD Zen5 platform enablement Robert Richter
2025-02-18 13:23 ` [PATCH v2 01/15] cxl: Modify address translation callback for generic use Robert Richter
2025-02-20 16:00   ` Gregory Price
2025-02-20 21:03     ` Dave Jiang
2025-02-18 13:23 ` [PATCH v2 02/15] cxl: Introduce callback to translate an HPA range from a port to its parent Robert Richter
2025-02-20 21:19   ` Dave Jiang
2025-02-18 13:23 ` [PATCH v2 03/15] cxl/region: Factor out code for interleaving calculations Robert Richter
2025-02-20 16:28   ` Gregory Price
2025-02-20 16:41     ` Gregory Price
2025-03-14 12:45   ` Jonathan Cameron
2025-02-18 13:23 ` [PATCH v2 04/15] cxl/region: Calculate endpoint's region position during init Robert Richter
2025-02-19 23:32   ` Gregory Price
2025-02-20 17:31   ` Gregory Price
2025-02-20 21:56   ` Dave Jiang
2025-04-04  4:38   ` Gregory Price
2025-04-04 15:36   ` [PATCH] cxl/region: Continue recalculating position during sort Gregory Price
2025-04-04 17:22     ` Gregory Price
2025-04-05  2:35   ` [PATCH] cxl region: recalculate interleave pos during region probe Gregory Price
2025-04-08 15:30     ` Gregory Price
2025-02-18 13:23 ` [PATCH v2 05/15] cxl/region: Calculate and store the SPA range of an endpoint Robert Richter
2025-02-20 18:42   ` Gregory Price
2025-02-20 22:31   ` Dave Jiang
2025-02-20 22:37     ` Gregory Price
2025-03-14 12:41   ` Jonathan Cameron
2025-02-18 13:23 ` [PATCH v2 06/15] cxl/region: Use endpoint's HPA range to find the port's decoder Robert Richter
2025-04-24  0:28   ` Gregory Price
2025-04-24 21:49     ` Gregory Price
2025-04-24 23:46       ` Gregory Price
2025-02-18 13:23 ` [PATCH v2 07/15] cxl/region: Use translated HPA ranges " Robert Richter
2025-02-20 19:13   ` Gregory Price
2025-02-18 13:23 ` [PATCH v2 08/15] cxl/region: Use the endpoint's SPA range to find a region Robert Richter
2025-02-20 19:28   ` Gregory Price
2025-03-14 12:45   ` Jonathan Cameron
2025-04-08 15:45   ` Gregory Price
2025-02-18 13:23 ` [PATCH v2 09/15] cxl/region: Use the endpoint's SPA range to create " Robert Richter
2025-02-20 19:31   ` Gregory Price
2025-03-14 12:46   ` Jonathan Cameron
2025-04-08 15:50   ` Gregory Price
2025-02-18 13:23 ` [PATCH v2 10/15] cxl/region: Use root decoders interleaving parameters " Robert Richter
2025-02-20 19:43   ` Gregory Price
2025-03-14 12:49   ` Jonathan Cameron
2025-04-01  1:59   ` Gregory Price
2025-04-01  5:26     ` Gregory Price
2025-04-01 18:03   ` Gregory Price
2025-02-18 13:23 ` [PATCH v2 11/15] cxl/region: Use the endpoint's SPA range to check " Robert Richter
2025-02-20 19:50   ` Gregory Price
2025-04-08 15:54   ` Gregory Price
2025-02-18 13:23 ` [PATCH v2 12/15] cxl/region: Lock decoders that need address translation Robert Richter
2025-02-20 19:57   ` Gregory Price
2025-02-18 13:23 ` Robert Richter [this message]
2025-02-20 19:57   ` [PATCH v2 13/15] cxl/x86: Prepare for architectural platform setup Gregory Price
2025-02-18 13:23 ` [PATCH v2 14/15] cxl/amd: Enable Zen5 address translation using ACPI PRMT Robert Richter
2025-02-21  0:40   ` Dave Jiang
2025-03-14 13:01   ` Jonathan Cameron
2025-04-05  2:38   ` [PATCH] [HACK] drop zen5_init checks due to segfault Gregory Price
2025-05-13 21:10     ` Robert Richter
2025-06-17 20:33       ` Joshua Hahn
2025-06-24  5:43         ` Robert Richter
2025-06-24 21:46           ` Joshua Hahn
2025-02-18 13:23 ` [PATCH v2 15/15] MAINTAINERS: CXL: Add entry for AMD platform support (CXL_AMD) Robert Richter
2025-02-20  1:00 ` [PATCH v2 00/15] cxl: Address translation support, part 2: Generic support and AMD Zen5 platform enablement Gregory Price

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