From: Gregory Price <gourry@gourry.net>
To: Robert Richter <rrichter@amd.com>
Cc: Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Dave Jiang <dave.jiang@intel.com>,
Davidlohr Bueso <dave@stgolabs.net>,
linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org,
"Fabio M. De Francesco" <fabio.m.de.francesco@linux.intel.com>,
Terry Bowman <terry.bowman@amd.com>
Subject: Re: [PATCH v2 06/15] cxl/region: Use endpoint's HPA range to find the port's decoder
Date: Wed, 23 Apr 2025 20:28:03 -0400 [thread overview]
Message-ID: <aAmFk1iQcS7UpslQ@gourry-fedora-PF4VCD3F> (raw)
In-Reply-To: <20250218132356.1809075-7-rrichter@amd.com>
On Tue, Feb 18, 2025 at 02:23:47PM +0100, Robert Richter wrote:
> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> index d898c9f51113..5048511f9de5 100644
> --- a/drivers/cxl/core/region.c
> +++ b/drivers/cxl/core/region.c
> @@ -906,7 +905,7 @@ cxl_find_decoder_early(struct cxl_port *port,
> return &cxled->cxld;
>
> if (test_bit(CXL_REGION_F_AUTO, &cxlr->flags))
> - dev = device_find_child(&port->dev, &cxlr->params,
> + dev = device_find_child(&port->dev, &cxled->cxld.hpa_range,
> match_auto_decoder);
This semantic has now changed because of the linear caching set.
Working around this with something like this hack for now
Probably we want to pull the range out of the resource and put it right
in the params instead of the local variable, but just getting it working
for testing for now
~Gregory
---
diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
index eac873125e6d..c8d38ce55045 100644
--- a/drivers/cxl/core/region.c
+++ b/drivers/cxl/core/region.c
@@ -833,7 +833,8 @@ static int match_free_decoder(struct device *dev, const void *data)
}
static bool region_res_match_cxl_range(const struct cxl_region_params *p,
- struct range *range)
+ const struct range *range1,
+ const struct range *range2)
{
if (!p->res)
return false;
@@ -843,8 +844,8 @@ static bool region_res_match_cxl_range(const struct cxl_region_params *p,
* to be fronted by the DRAM range in current known implementation.
* This assumption will be made until a variant implementation exists.
*/
- return p->res->start + p->cache_size == range->start &&
- p->res->end == range->end;
+ return range1->start + p->cache_size == range2->start &&
+ range1->end == range2->end;
}
static int cxl_port_calc_hpa(struct cxl_port *port, struct cxl_decoder *cxld,
@@ -885,11 +886,15 @@ static int cxl_port_calc_hpa(struct cxl_port *port, struct cxl_decoder *cxld,
return 1;
}
+struct mad_context {
+ struct cxl_region_params *p;
+ struct range *r;
+};
static int match_auto_decoder(struct device *dev, const void *data)
{
- const struct cxl_region_params *p = data;
+ const struct range *r;
struct cxl_decoder *cxld;
- struct range *r;
+ const struct mad_context *ctx = data;
if (!is_switch_decoder(dev))
return 0;
@@ -897,7 +902,7 @@ static int match_auto_decoder(struct device *dev, const void *data)
cxld = to_cxl_decoder(dev);
r = &cxld->hpa_range;
- if (region_res_match_cxl_range(p, r))
+ if (region_res_match_cxl_range(ctx->p, ctx->r, r))
return 1;
return 0;
@@ -916,13 +921,14 @@ cxl_find_decoder_early(struct cxl_port *port,
struct cxl_region *cxlr)
{
struct device *dev;
+ struct mad_context mad = { .p = &cxlr->params,
+ .r =&cxled->cxld.hpa_range };
if (port == cxled_to_port(cxled))
return &cxled->cxld;
if (test_bit(CXL_REGION_F_AUTO, &cxlr->flags))
- dev = device_find_child(&port->dev, &cxlr->params,
- match_auto_decoder);
+ dev = device_find_child(&port->dev, &mad, match_auto_decoder);
else
dev = device_find_child(&port->dev, NULL, match_free_decoder);
if (!dev)
@@ -1363,6 +1369,7 @@ static int cxl_port_setup_targets(struct cxl_port *port,
struct cxl_decoder *cxld = cxl_rr->decoder;
struct cxl_switch_decoder *cxlsd;
struct cxl_port *iter = port;
+ struct range r;
u16 eig, peig;
u8 eiw, peiw;
@@ -1488,10 +1495,12 @@ static int cxl_port_setup_targets(struct cxl_port *port,
return -ENXIO;
}
+ r.start = p ? p->res->start : 0;
+ r.end = p ? p->res->end : 0;
if (test_bit(CXL_REGION_F_AUTO, &cxlr->flags)) {
if (cxld->interleave_ways != iw ||
cxld->interleave_granularity != ig ||
- !region_res_match_cxl_range(p, &cxld->hpa_range) ||
+ !region_res_match_cxl_range(p, &r, &cxld->hpa_range) ||
((cxld->flags & CXL_DECODER_F_ENABLE) == 0)) {
dev_err(&cxlr->dev,
"%s:%s %s expected iw: %d ig: %d %pr\n",
next prev parent reply other threads:[~2025-04-24 0:28 UTC|newest]
Thread overview: 61+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-18 13:23 [PATCH v2 00/15] cxl: Address translation support, part 2: Generic support and AMD Zen5 platform enablement Robert Richter
2025-02-18 13:23 ` [PATCH v2 01/15] cxl: Modify address translation callback for generic use Robert Richter
2025-02-20 16:00 ` Gregory Price
2025-02-20 21:03 ` Dave Jiang
2025-02-18 13:23 ` [PATCH v2 02/15] cxl: Introduce callback to translate an HPA range from a port to its parent Robert Richter
2025-02-20 21:19 ` Dave Jiang
2025-02-18 13:23 ` [PATCH v2 03/15] cxl/region: Factor out code for interleaving calculations Robert Richter
2025-02-20 16:28 ` Gregory Price
2025-02-20 16:41 ` Gregory Price
2025-03-14 12:45 ` Jonathan Cameron
2025-02-18 13:23 ` [PATCH v2 04/15] cxl/region: Calculate endpoint's region position during init Robert Richter
2025-02-19 23:32 ` Gregory Price
2025-02-20 17:31 ` Gregory Price
2025-02-20 21:56 ` Dave Jiang
2025-04-04 4:38 ` Gregory Price
2025-04-04 15:36 ` [PATCH] cxl/region: Continue recalculating position during sort Gregory Price
2025-04-04 17:22 ` Gregory Price
2025-04-05 2:35 ` [PATCH] cxl region: recalculate interleave pos during region probe Gregory Price
2025-04-08 15:30 ` Gregory Price
2025-02-18 13:23 ` [PATCH v2 05/15] cxl/region: Calculate and store the SPA range of an endpoint Robert Richter
2025-02-20 18:42 ` Gregory Price
2025-02-20 22:31 ` Dave Jiang
2025-02-20 22:37 ` Gregory Price
2025-03-14 12:41 ` Jonathan Cameron
2025-02-18 13:23 ` [PATCH v2 06/15] cxl/region: Use endpoint's HPA range to find the port's decoder Robert Richter
2025-04-24 0:28 ` Gregory Price [this message]
2025-04-24 21:49 ` Gregory Price
2025-04-24 23:46 ` Gregory Price
2025-02-18 13:23 ` [PATCH v2 07/15] cxl/region: Use translated HPA ranges " Robert Richter
2025-02-20 19:13 ` Gregory Price
2025-02-18 13:23 ` [PATCH v2 08/15] cxl/region: Use the endpoint's SPA range to find a region Robert Richter
2025-02-20 19:28 ` Gregory Price
2025-03-14 12:45 ` Jonathan Cameron
2025-04-08 15:45 ` Gregory Price
2025-02-18 13:23 ` [PATCH v2 09/15] cxl/region: Use the endpoint's SPA range to create " Robert Richter
2025-02-20 19:31 ` Gregory Price
2025-03-14 12:46 ` Jonathan Cameron
2025-04-08 15:50 ` Gregory Price
2025-02-18 13:23 ` [PATCH v2 10/15] cxl/region: Use root decoders interleaving parameters " Robert Richter
2025-02-20 19:43 ` Gregory Price
2025-03-14 12:49 ` Jonathan Cameron
2025-04-01 1:59 ` Gregory Price
2025-04-01 5:26 ` Gregory Price
2025-04-01 18:03 ` Gregory Price
2025-02-18 13:23 ` [PATCH v2 11/15] cxl/region: Use the endpoint's SPA range to check " Robert Richter
2025-02-20 19:50 ` Gregory Price
2025-04-08 15:54 ` Gregory Price
2025-02-18 13:23 ` [PATCH v2 12/15] cxl/region: Lock decoders that need address translation Robert Richter
2025-02-20 19:57 ` Gregory Price
2025-02-18 13:23 ` [PATCH v2 13/15] cxl/x86: Prepare for architectural platform setup Robert Richter
2025-02-20 19:57 ` Gregory Price
2025-02-18 13:23 ` [PATCH v2 14/15] cxl/amd: Enable Zen5 address translation using ACPI PRMT Robert Richter
2025-02-21 0:40 ` Dave Jiang
2025-03-14 13:01 ` Jonathan Cameron
2025-04-05 2:38 ` [PATCH] [HACK] drop zen5_init checks due to segfault Gregory Price
2025-05-13 21:10 ` Robert Richter
2025-06-17 20:33 ` Joshua Hahn
2025-06-24 5:43 ` Robert Richter
2025-06-24 21:46 ` Joshua Hahn
2025-02-18 13:23 ` [PATCH v2 15/15] MAINTAINERS: CXL: Add entry for AMD platform support (CXL_AMD) Robert Richter
2025-02-20 1:00 ` [PATCH v2 00/15] cxl: Address translation support, part 2: Generic support and AMD Zen5 platform enablement Gregory Price
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