From: Robert Richter <rrichter@amd.com>
To: Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Dave Jiang <dave.jiang@intel.com>,
Davidlohr Bueso <dave@stgolabs.net>
Cc: <linux-cxl@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Gregory Price <gourry@gourry.net>,
Terry Bowman <terry.bowman@amd.com>,
Robert Richter <rrichter@amd.com>
Subject: [PATCH 1/2] cxl/pci: Ignore downstream ports with duplicate port IDs
Date: Wed, 5 Mar 2025 11:01:22 +0100 [thread overview]
Message-ID: <20250305100123.3077031-2-rrichter@amd.com> (raw)
In-Reply-To: <20250305100123.3077031-1-rrichter@amd.com>
If a link is inactive, the port ID in the PCIe Link Capability
Register of a downstream port may not be assigned yet. Another
downstream port with an inactive link on the same Downstream Switch
Port may have the same port ID. In this case the port enumeration of
the root or downstream port fails due to duplicate port IDs
(devm_cxl_port_enumerate_dports()/add_dport()).
Relax the check and just ignore downstream ports with duplicate port
IDs. Do not fail and continue to enumerate all downstream ports of a
CXL Root Port or CXL Switch. Turn the related dev_err() messages into
a dev_dbg().
Signed-off-by: Robert Richter <rrichter@amd.com>
---
drivers/cxl/core/pci.c | 10 ++++++++--
drivers/cxl/core/port.c | 2 +-
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index fbc50b1156b8..524b8749cc0b 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -59,8 +59,14 @@ static int match_add_dports(struct pci_dev *pdev, void *data)
port_num = FIELD_GET(PCI_EXP_LNKCAP_PN, lnkcap);
dport = devm_cxl_add_dport(port, &pdev->dev, port_num, map.resource);
if (IS_ERR(dport)) {
- ctx->error = PTR_ERR(dport);
- return PTR_ERR(dport);
+ rc = PTR_ERR(dport);
+ if (rc == -EBUSY) {
+ dev_dbg(&port->dev, "failed to add dport %s, continuing\n",
+ dev_name(&pdev->dev));
+ return 0;
+ }
+ ctx->error = rc;
+ return rc;
}
ctx->count++;
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 33607301c5d3..8038cbeffbf7 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -1071,7 +1071,7 @@ static int add_dport(struct cxl_port *port, struct cxl_dport *dport)
device_lock_assert(&port->dev);
dup = find_dport(port, dport->port_id);
if (dup) {
- dev_err(&port->dev,
+ dev_dbg(&port->dev,
"unable to add dport%d-%s non-unique port id (%s)\n",
dport->port_id, dev_name(dport->dport_dev),
dev_name(dup->dport_dev));
--
2.39.5
next prev parent reply other threads:[~2025-03-05 10:08 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-05 10:01 [PATCH 0/2] cxl/pci: Inactive downstream port handling Robert Richter
2025-03-05 10:01 ` Robert Richter [this message]
2025-03-05 15:09 ` [PATCH 1/2] cxl/pci: Ignore downstream ports with duplicate port IDs Ira Weiny
2025-03-07 15:28 ` Robert Richter
2025-03-14 12:11 ` Jonathan Cameron
2025-03-05 10:01 ` [PATCH 2/2] cxl/pci: Check link status and only enable active dports Robert Richter
2025-03-05 15:19 ` Ira Weiny
2025-03-07 15:43 ` Robert Richter
2025-03-07 20:51 ` Ira Weiny
2025-03-14 12:14 ` Jonathan Cameron
2025-03-05 19:06 ` [PATCH 0/2] cxl/pci: Inactive downstream port handling Dan Williams
2025-03-07 14:06 ` Robert Richter
2025-03-07 20:58 ` Dan Williams
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