Re: [RFC Patch v1 2/3] cxl/pci: Update Port GPF timeout only when the first EP attaching

[Jonathan Cameron <Jonathan.Cameron@huawei.com>]

On Thu, 20 Mar 2025 22:40:07 -0700
Davidlohr Bueso <dave@stgolabs.net> wrote:

> On Wed, 19 Mar 2025, Li Ming wrote:
> 
> >If a CXL switch is under a CXL root port, The Port GPF Phase timeout
> >will be updated on the CXL root port when each cxl memory device under
> >the CXL switch is attaching. It is possible to be updated more than
> >once. Actually, it is enough to initialize once, other extra
> >initializations are redundant.  
> 
> It's actually not updated more than necessary because update_gpf_port_dvsec()
> checks first:
> 
> 	if (FIELD_GET(base, ctrl) == GPF_TIMEOUT_BASE_MAX &&
> 	    FIELD_GET(scale, ctrl) == GPF_TIMEOUT_SCALE_MAX)
> 		return 0;
> 
> >When the first EP attaching, it always triggers its ancestor dports to
> >locate their own Port GPF DVSEC. The change is that updating Port GPF
> >Phase timeout on these ancestor dports after ancestor dport locating a
> >Port GPF DVSEC. It guaranttess that Port GPF Phase timeout updating on a  
> 
> s/guaranttess/guarantees
> 
> >dport only happens during the first EP attaching.  
> 
> ... but yeah, I think this is still better, logically.
> 
> Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
Agree that this seems sensible.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> 
> (with the caveat that if patch 1 is not necessary then this would need to
> be redone).