From: Dan Williams <dan.j.williams@intel.com>
To: Li Ming <ming.li@zohomail.com>, <dave@stgolabs.net>,
<jonathan.cameron@huawei.com>, <dave.jiang@intel.com>,
<alison.schofield@intel.com>, <vishal.l.verma@intel.com>,
<ira.weiny@intel.com>, <dan.j.williams@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Li Ming <ming.li@zohomail.com>
Subject: Re: [RFC Patch v1 0/3] Fix using wrong GPF DVSEC location issue
Date: Fri, 21 Mar 2025 10:02:16 -0700 [thread overview]
Message-ID: <67dd9b9873189_11987294ed@dwillia2-xfh.jf.intel.com.notmuch> (raw)
In-Reply-To: <20250319035516.222054-1-ming.li@zohomail.com>
Li Ming wrote:
> During review all new patches in branch cxl/next. I noticed there may be
> a problem in below commit.
>
> commit a52b6a2c1c99 ("cxl/pci: Support Global Persistent Flush (GPF)")
>
> There is a new field gpf_dvsec in struct cxl_port to cache GPF DVSEC for
> Port(DVSEC ID 04h) location. When the first EP attaching to a cxl port,
> it will trigger locating GPF DVSEC on the cxl dport which the first EP
> is under, then the location is cached in port->gpf_dvsec. So if another
> EP under another dport is attaching, it will reuse the value of
> port->gpf_dvsec as GPF DVSEC location for this another dport. The
> problem is the cached location may be a wrong location for other dports
> of the port.
>
> Per Table 8-2 in CXL r3.2 section 8.1.1 and CXL r3.2 section 8.1.6, Each
> CXL Downstream switch ports and CXL root ports have their own GPF DVSEC
> for Port(DVSEC ID 04h). So my understanding is that CXL subsystem should
> locate GPF DVSEC for Port for each dport rather than using the cached
> location in CXL port.
>
> But I am not sure if all dports under a same port will have same
> configuration space layout, if yes, that will not be a problem. If I am
> wrong, please let me know, thanks.
>
> base-commit: 3b5d43245f0a56390baaa670e1b6d898772266b3 cxl/next
>
> Li Ming (3):
> cxl/core: Fix caching dport GPF DVSEC issue
> cxl/pci: Update Port GPF timeout only when the first EP attaching
> cxl/pci: Drop the parameter is_port of cxl_gpf_get_dvsec()
These look good. I doubt a device would build different offsets
per-dport, but the real risk is more in confusing future code readers
that dports are uniform.
For the series,
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
A Fixes tag seems reasonable.
prev parent reply other threads:[~2025-03-21 17:02 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-19 3:55 [RFC Patch v1 0/3] Fix using wrong GPF DVSEC location issue Li Ming
2025-03-19 3:55 ` [RFC Patch v1 1/3] cxl/core: Fix caching dport GPF DVSEC issue Li Ming
2025-03-21 7:41 ` Davidlohr Bueso
2025-03-21 12:08 ` Jonathan Cameron
2025-03-19 3:55 ` [RFC Patch v1 2/3] cxl/pci: Update Port GPF timeout only when the first EP attaching Li Ming
2025-03-21 5:40 ` Davidlohr Bueso
2025-03-21 12:07 ` Jonathan Cameron
2025-03-19 3:55 ` [RFC Patch v1 3/3] cxl/pci: Drop the parameter is_port of cxl_gpf_get_dvsec() Li Ming
2025-03-21 5:23 ` Davidlohr Bueso
2025-03-21 12:06 ` Jonathan Cameron
2025-03-21 2:14 ` [RFC Patch v1 0/3] Fix using wrong GPF DVSEC location issue Davidlohr Bueso
2025-03-21 3:59 ` Davidlohr Bueso
2025-03-21 6:55 ` Li Ming
2025-03-21 12:09 ` Jonathan Cameron
2025-03-21 17:02 ` Dan Williams [this message]
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