From: Dave Jiang <dave.jiang@intel.com>
To: linux-cxl@vger.kernel.org
Cc: dave@stgolabs.net, jonathan.cameron@huawei.com,
alison.schofield@intel.com, vishal.l.verma@intel.com,
ira.weiny@intel.com, dan.j.williams@intel.com, gourry@gourry.net
Subject: [PATCH v2 2/3] cxl: docs/platform/acpi/srat Add generic target documentation
Date: Wed, 14 May 2025 17:09:22 -0700 [thread overview]
Message-ID: <20250515000923.2590820-3-dave.jiang@intel.com> (raw)
In-Reply-To: <20250515000923.2590820-1-dave.jiang@intel.com>
Add description in the SRAT document to descript the Generic Port
Affinity sub-table.
Reviewed-by: Gregory Price <gourry@gourry.net>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
---
v2:
- Clarify sentence in usage description. (Gregory)
- Added association of SRAT to HMAT.
---
.../driver-api/cxl/platform/acpi/srat.rst | 27 +++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/Documentation/driver-api/cxl/platform/acpi/srat.rst b/Documentation/driver-api/cxl/platform/acpi/srat.rst
index 56d7bbb18c3b..cc98ca0e508e 100644
--- a/Documentation/driver-api/cxl/platform/acpi/srat.rst
+++ b/Documentation/driver-api/cxl/platform/acpi/srat.rst
@@ -42,3 +42,30 @@ Example ::
Enabled : 1
Hot Pluggable : 1
Non-Volatile : 0
+
+
+Generic Port Affinity
+=====================
+The Generic Port Affinity subtable provides an association between a proximity
+domain and a device handle representing a Generic Port such as a CXL host
+bridge. With the association, latency and bandwidth numbers can be retrieved
+from the SRAT for the path between CPU(s) (initiator) and the Generic Port.
+This is used to construct performance coordinates for hotplugged CXL DEVICES,
+which cannot be enumerated at boot by platform firmware.
+
+Example ::
+
+ Subtable Type : 06 [Generic Port Affinity]
+ Length : 20 <- 32d, length of table
+ Reserved : 00
+ Device Handle Type : 00 <- 0 - ACPI, 1 - PCI
+ Proximity Domain : 00000001
+ Device Handle : ACPI0016:01
+ Flags : 00000001 <- Bit 0 (Enabled)
+ Reserved : 00000000
+
+The Proximity Domain is matched up to the :doc:`HMAT <hmat>` SSLBI Target
+Proximity Domain List for the related latency or bandwidth numbers. Those
+performance numbers are tied to a CXL host bridge via the Device Handle.
+The driver uses the association to retrieve the Generic Port performance
+numbers for the whole CXL path access coordinates calculation.
--
2.49.0
next prev parent reply other threads:[~2025-05-15 0:09 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-15 0:09 [PATCH v2 0/3] cxl: Update CXL documentation for access coordinates calculation Dave Jiang
2025-05-15 0:09 ` [PATCH v2 1/3] cxl: docs/platform/cdat reference documentation Dave Jiang
2025-05-15 3:41 ` Gregory Price
2025-05-15 0:09 ` Dave Jiang [this message]
2025-05-15 0:09 ` [PATCH v2 3/3] cxl: doc/linux/access-coordinates Update access coordinates calculation methods Dave Jiang
2025-05-15 17:15 ` [PATCH v2 0/3] cxl: Update CXL documentation for access coordinates calculation Alison Schofield
2025-05-15 17:25 ` Dave Jiang
2025-05-15 23:51 ` Dave Jiang
2025-05-19 15:42 ` Jonathan Cameron
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