[PATCH v2 0/3] cxl: Update CXL documentation for access coordinates calculation

[PATCH v2 0/3] cxl: Update CXL documentation for access coordinates calculation

[Dave Jiang]

v2:
- Language clarifications (Gregory)
- Move all CDAT bits into single document. (Gregory)
- Define CDAT terms. (Gregory)

Add CXL access coordinates calculation documentation including CDAT details.


Dave Jiang (3):
  cxl: docs/platform/cdat reference documentation
  cxl: docs/platform/acpi/srat Add generic target documentation
  cxl: doc/linux/access-coordinates Update access coordinates
    calculation methods

 Documentation/driver-api/cxl/index.rst        |   1 +
 .../cxl/linux/access-coordinates.rst          |  86 +++++++++++++
 .../driver-api/cxl/platform/acpi/srat.rst     |  27 ++++
 .../driver-api/cxl/platform/cdat.rst          | 118 ++++++++++++++++++
 4 files changed, 232 insertions(+)
 create mode 100644 Documentation/driver-api/cxl/platform/cdat.rst


base-commit: 7855bc1362518673103bd9357827572207e6f6d9
-- 
2.49.0

[PATCH v2 1/3] cxl: docs/platform/cdat reference documentation

[Dave Jiang]

Add documentation for CDAT structures for CXL usages.

Signed-off-by: Dave Jiang <dave.jiang@intel.com>

---
v2:
- Move everything into cdat.rst (Gregory)
- Update various languages in the doc for clarification (Gregory)
- Add a term definition section (Gregory)
---
 Documentation/driver-api/cxl/index.rst        |   1 +
 .../driver-api/cxl/platform/cdat.rst          | 118 ++++++++++++++++++
 2 files changed, 119 insertions(+)
 create mode 100644 Documentation/driver-api/cxl/platform/cdat.rst

diff --git a/Documentation/driver-api/cxl/index.rst b/Documentation/driver-api/cxl/index.rst
index 366faf851fc7..9e1414ad3357 100644
--- a/Documentation/driver-api/cxl/index.rst
+++ b/Documentation/driver-api/cxl/index.rst
@@ -27,6 +27,7 @@ that have impacts on each other.  The docs here break up configurations steps.
 
    platform/bios-and-efi
    platform/acpi
+   platform/cdat
    platform/example-configs
 
 .. toctree::
diff --git a/Documentation/driver-api/cxl/platform/cdat.rst b/Documentation/driver-api/cxl/platform/cdat.rst
new file mode 100644
index 000000000000..34bbe7264d71
--- /dev/null
+++ b/Documentation/driver-api/cxl/platform/cdat.rst
@@ -0,0 +1,118 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+======================================
+Coherent Device Attribute Table (CDAT)
+======================================
+
+The CDAT provides functional and performance attributes of devices such
+as CXL accelerators, switches, or endpoints.  The table formatting is
+similar to ACPI tables. CDAT data may be parsed by BIOS at boot or may
+be enumerated at runtime (after device hotplug, for example).
+
+Terminology:
+DPA - Device Physical Address, used by the CXL device to denote the address
+it supports for that device.
+
+DSMADHandle - A device unique handle that is associated with a DPA range
+defined by the DSMAS table.
+
+
+===============================================
+Device Scoped Memory Affinity Structure (DSMAS)
+===============================================
+
+The DSMAS contains information such as DSMADHandle, the DPA Base, and DPA
+Length.
+
+This table is used by Linux in conjunction with the Device Scoped Latency and
+Bandwidth Information Structure (DSLBIS) to determine the performance
+attributes of the CXL device itself.
+
+Example ::
+
+ Structure Type : 00 [DSMAS]
+       Reserved : 00
+         Length : 0018              <- 24d, size of structure
+    DSMADHandle : 01
+          Flags : 00
+       Reserved : 0000
+       DPA Base : 0000000040000000  <- 1GiB base
+     DPA Length : 0000000080000000  <- 2GiB size
+
+
+==================================================================
+Device Scoped Latency and Bandwidth Information Structure (DSLBIS)
+==================================================================
+
+This table is used by Linux in conjunction with DSMAS to determine the
+performance attributes of a CXL device.  The DSLBIS contains latency
+and bandwidth information based on DSMADHandle matching.
+
+Example ::
+
+   Structure Type : 01 [DSLBIS]
+         Reserved : 00
+           Length : 18                     <- 24d, size of structure
+           Handle : 0001                   <- DSMAS handle
+            Flags : 00                     <- Matches flag field for HMAT SLLBIS
+        Data Type : 00                     <- Latency
+ Entry Basee Unit : 0000000000001000       <- Entry Base Unit field in HMAT SSLBIS
+            Entry : 010000000000           <- First byte used here, CXL LTC
+         Reserved : 0000
+
+   Structure Type : 01 [DSLBIS]
+         Reserved : 00
+           Length : 18                     <- 24d, size of structure
+           Handle : 0001                   <- DSMAS handle
+            Flags : 00                     <- Matches flag field for HMAT SLLBIS
+        Data Type : 03                     <- Bandwidth
+ Entry Basee Unit : 0000000000001000       <- Entry Base Unit field in HMAT SSLBIS
+            Entry : 020000000000           <- First byte used here, CXL BW
+         Reserved : 0000
+
+
+==================================================================
+Switch Scoped Latency and Bandwidth Information Structure (SSLBIS)
+==================================================================
+
+The SSLBIS contains information about the latency and bandwidth of a switch.
+
+The table is used by Linux to compute the performance coordinates of a CXL path
+from the device to the root port where a switch is part of the path.
+
+Example ::
+
+  Structure Type : 05 [SSLBIS]
+        Reserved : 00
+          Length : 20                           <- 32d, length of record, including SSLB entries
+       Data Type : 00                           <- Latency
+        Reserved : 000000
+ Entry Base Unit : 00000000000000001000         <- Matches Entry Base Unit in HMAT SSLBIS
+
+                                                <- SSLB Entry 0
+       Port X ID : 0100                         <- First port, 0100h represents an upstream port
+       Port Y ID : 0000                         <- Second port, downstream port 0
+         Latency : 0100                         <- Port latency
+        Reserved : 0000
+                                                <- SSLB Entry 1
+       Port X ID : 0100
+       Port Y ID : 0001
+         Latency : 0100
+        Reserved : 0000
+
+
+  Structure Type : 05 [SSLBIS]
+        Reserved : 00
+          Length : 18                           <- 24d, length of record, including SSLB entry
+       Data Type : 03                           <- Bandwidth
+        Reserved : 000000
+ Entry Base Unit : 00000000000000001000         <- Matches Entry Base Unit in HMAT SSLBIS
+
+                                                <- SSLB Entry 0
+       Port X ID : 0100                         <- First port, 0100h represents an upstream port
+       Port Y ID : FFFF                         <- Second port, FFFFh indicates any port
+       Bandwidth : 1200                         <- Port bandwidth
+        Reserved : 0000
+
+The CXL driver uses a combination of CDAT, HMAT, SRAT, and other data to
+generate "whole path performance" data for a CXL device.
-- 
2.49.0

Re: [PATCH v2 1/3] cxl: docs/platform/cdat reference documentation

[Gregory Price]

On Wed, May 14, 2025 at 05:09:21PM -0700, Dave Jiang wrote:
> Add documentation for CDAT structures for CXL usages.
> 
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
>

Reviewed-by: Gregory Price <gourry@gourry.net>

> ---
> v2:
> - Move everything into cdat.rst (Gregory)
> - Update various languages in the doc for clarification (Gregory)
> - Add a term definition section (Gregory)
> ---
>  Documentation/driver-api/cxl/index.rst        |   1 +
>  .../driver-api/cxl/platform/cdat.rst          | 118 ++++++++++++++++++
>  2 files changed, 119 insertions(+)
>  create mode 100644 Documentation/driver-api/cxl/platform/cdat.rst
> 
> diff --git a/Documentation/driver-api/cxl/index.rst b/Documentation/driver-api/cxl/index.rst
> index 366faf851fc7..9e1414ad3357 100644
> --- a/Documentation/driver-api/cxl/index.rst
> +++ b/Documentation/driver-api/cxl/index.rst
> @@ -27,6 +27,7 @@ that have impacts on each other.  The docs here break up configurations steps.
>  
>     platform/bios-and-efi
>     platform/acpi
> +   platform/cdat
>     platform/example-configs
>  
>  .. toctree::
> diff --git a/Documentation/driver-api/cxl/platform/cdat.rst b/Documentation/driver-api/cxl/platform/cdat.rst
> new file mode 100644
> index 000000000000..34bbe7264d71
> --- /dev/null
> +++ b/Documentation/driver-api/cxl/platform/cdat.rst
> @@ -0,0 +1,118 @@
> +.. SPDX-License-Identifier: GPL-2.0
> +
> +======================================
> +Coherent Device Attribute Table (CDAT)
> +======================================
> +
> +The CDAT provides functional and performance attributes of devices such
> +as CXL accelerators, switches, or endpoints.  The table formatting is
> +similar to ACPI tables. CDAT data may be parsed by BIOS at boot or may
> +be enumerated at runtime (after device hotplug, for example).
> +
> +Terminology:
> +DPA - Device Physical Address, used by the CXL device to denote the address
> +it supports for that device.
> +
> +DSMADHandle - A device unique handle that is associated with a DPA range
> +defined by the DSMAS table.
> +
> +
> +===============================================
> +Device Scoped Memory Affinity Structure (DSMAS)
> +===============================================
> +
> +The DSMAS contains information such as DSMADHandle, the DPA Base, and DPA
> +Length.
> +
> +This table is used by Linux in conjunction with the Device Scoped Latency and
> +Bandwidth Information Structure (DSLBIS) to determine the performance
> +attributes of the CXL device itself.
> +
> +Example ::
> +
> + Structure Type : 00 [DSMAS]
> +       Reserved : 00
> +         Length : 0018              <- 24d, size of structure
> +    DSMADHandle : 01
> +          Flags : 00
> +       Reserved : 0000
> +       DPA Base : 0000000040000000  <- 1GiB base
> +     DPA Length : 0000000080000000  <- 2GiB size
> +
> +
> +==================================================================
> +Device Scoped Latency and Bandwidth Information Structure (DSLBIS)
> +==================================================================
> +
> +This table is used by Linux in conjunction with DSMAS to determine the
> +performance attributes of a CXL device.  The DSLBIS contains latency
> +and bandwidth information based on DSMADHandle matching.
> +
> +Example ::
> +
> +   Structure Type : 01 [DSLBIS]
> +         Reserved : 00
> +           Length : 18                     <- 24d, size of structure
> +           Handle : 0001                   <- DSMAS handle
> +            Flags : 00                     <- Matches flag field for HMAT SLLBIS
> +        Data Type : 00                     <- Latency
> + Entry Basee Unit : 0000000000001000       <- Entry Base Unit field in HMAT SSLBIS
> +            Entry : 010000000000           <- First byte used here, CXL LTC
> +         Reserved : 0000
> +
> +   Structure Type : 01 [DSLBIS]
> +         Reserved : 00
> +           Length : 18                     <- 24d, size of structure
> +           Handle : 0001                   <- DSMAS handle
> +            Flags : 00                     <- Matches flag field for HMAT SLLBIS
> +        Data Type : 03                     <- Bandwidth
> + Entry Basee Unit : 0000000000001000       <- Entry Base Unit field in HMAT SSLBIS
> +            Entry : 020000000000           <- First byte used here, CXL BW
> +         Reserved : 0000
> +
> +
> +==================================================================
> +Switch Scoped Latency and Bandwidth Information Structure (SSLBIS)
> +==================================================================
> +
> +The SSLBIS contains information about the latency and bandwidth of a switch.
> +
> +The table is used by Linux to compute the performance coordinates of a CXL path
> +from the device to the root port where a switch is part of the path.
> +
> +Example ::
> +
> +  Structure Type : 05 [SSLBIS]
> +        Reserved : 00
> +          Length : 20                           <- 32d, length of record, including SSLB entries
> +       Data Type : 00                           <- Latency
> +        Reserved : 000000
> + Entry Base Unit : 00000000000000001000         <- Matches Entry Base Unit in HMAT SSLBIS
> +
> +                                                <- SSLB Entry 0
> +       Port X ID : 0100                         <- First port, 0100h represents an upstream port
> +       Port Y ID : 0000                         <- Second port, downstream port 0
> +         Latency : 0100                         <- Port latency
> +        Reserved : 0000
> +                                                <- SSLB Entry 1
> +       Port X ID : 0100
> +       Port Y ID : 0001
> +         Latency : 0100
> +        Reserved : 0000
> +
> +
> +  Structure Type : 05 [SSLBIS]
> +        Reserved : 00
> +          Length : 18                           <- 24d, length of record, including SSLB entry
> +       Data Type : 03                           <- Bandwidth
> +        Reserved : 000000
> + Entry Base Unit : 00000000000000001000         <- Matches Entry Base Unit in HMAT SSLBIS
> +
> +                                                <- SSLB Entry 0
> +       Port X ID : 0100                         <- First port, 0100h represents an upstream port
> +       Port Y ID : FFFF                         <- Second port, FFFFh indicates any port
> +       Bandwidth : 1200                         <- Port bandwidth
> +        Reserved : 0000
> +
> +The CXL driver uses a combination of CDAT, HMAT, SRAT, and other data to
> +generate "whole path performance" data for a CXL device.
> -- 
> 2.49.0
> 

[PATCH v2 2/3] cxl: docs/platform/acpi/srat Add generic target documentation

[Dave Jiang]

Add description in the SRAT document to descript the Generic Port
Affinity sub-table.

Reviewed-by: Gregory Price <gourry@gourry.net>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
---
v2:
- Clarify sentence in usage description. (Gregory)
- Added association of SRAT to HMAT.
---
 .../driver-api/cxl/platform/acpi/srat.rst     | 27 +++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/Documentation/driver-api/cxl/platform/acpi/srat.rst b/Documentation/driver-api/cxl/platform/acpi/srat.rst
index 56d7bbb18c3b..cc98ca0e508e 100644
--- a/Documentation/driver-api/cxl/platform/acpi/srat.rst
+++ b/Documentation/driver-api/cxl/platform/acpi/srat.rst
@@ -42,3 +42,30 @@ Example ::
               Enabled : 1
         Hot Pluggable : 1
          Non-Volatile : 0
+
+
+Generic Port Affinity
+=====================
+The Generic Port Affinity subtable provides an association between a proximity
+domain and a device handle representing a Generic Port such as a CXL host
+bridge. With the association, latency and bandwidth numbers can be retrieved
+from the SRAT for the path between CPU(s) (initiator) and the Generic Port.
+This is used to construct performance coordinates for hotplugged CXL DEVICES,
+which cannot be enumerated at boot by platform firmware.
+
+Example ::
+
+         Subtable Type : 06 [Generic Port Affinity]
+                Length : 20               <- 32d, length of table
+              Reserved : 00
+    Device Handle Type : 00               <- 0 - ACPI, 1 - PCI
+      Proximity Domain : 00000001
+         Device Handle : ACPI0016:01
+                 Flags : 00000001         <- Bit 0 (Enabled)
+              Reserved : 00000000
+
+The Proximity Domain is matched up to the :doc:`HMAT <hmat>` SSLBI Target
+Proximity Domain List for the related latency or bandwidth numbers. Those
+performance numbers are tied to a CXL host bridge via the Device Handle.
+The driver uses the association to retrieve the Generic Port performance
+numbers for the whole CXL path access coordinates calculation.
-- 
2.49.0

[PATCH v2 3/3] cxl: doc/linux/access-coordinates Update access coordinates calculation methods

[Dave Jiang]

Add documentation on how to calculate the access coordinates for a given
CXL region in detail.

Reviewed-by: Gregory Price <gourry@gourry.net>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
---
v2:
- Clarification of language. (Gregory)
---
 .../cxl/linux/access-coordinates.rst          | 86 +++++++++++++++++++
 1 file changed, 86 insertions(+)

diff --git a/Documentation/driver-api/cxl/linux/access-coordinates.rst b/Documentation/driver-api/cxl/linux/access-coordinates.rst
index 71024fa0f561..341a7c682043 100644
--- a/Documentation/driver-api/cxl/linux/access-coordinates.rst
+++ b/Documentation/driver-api/cxl/linux/access-coordinates.rst
@@ -5,6 +5,83 @@
 CXL Access Coordinates Computation
 ==================================
 
+Latency and Bandwidth Calculation
+=================================
+A memory region performance coordinates (latency and bandwidth) are typically
+provided via ACPI tables :doc:`SRAT <../platform/acpi/srat>` and
+:doc:`HMAT <../platform/acpi/hmat>`. However, the platform firmware (BIOS) is
+not able to annotate those for CXL devices that are hot-plugged since they do
+not exist during platform firmware initialization. The CXL driver can compute
+the performance coordinates by retrieving data from several components.
+
+The :doc:`SRAT <../platform/acpi/srat>` provides a Generic Port Affinity
+subtable that ties a proximity domain to a device handle, which in this case
+would be the CXL hostbridge. Using this association, the performance
+coordinates for the Generic Port can be retrieved from the
+:doc:`HMAT <../platform/acpi/hmat>` subtable. This piece represents the
+performance coordinates between a CPU and a Generic Port (CXL hostbridge).
+
+The :doc:`CDAT <../platform/cdat>` provides the performance coordinates for
+the CXL device itself. That is the bandwidth and latency to access that device's
+memory region. The DSMAS subtable provides a DSMADHandle that is tied to a
+Device Physical Address (DPA) range. The DSLBIS subtable provides the
+performance coordinates that's tied to a DSMADhandle and this ties the two
+table entries together to provide the performance coordinates for each DPA
+region. For example, if a device exports a DRAM region and a PMEM region,
+then there would be different performance characteristsics for each of those
+regions.
+
+If there's a CXL switch in the topology, then the performance coordinates for the
+switch is provided by SSLBIS subtable. This provides the bandwidth and latency
+for traversing the switch between the switch upstream port and the switch
+downstream port that points to the endpoint device.
+
+Simple topology example::
+
+ GP0/HB0/ACPI0016-0
+        RP0
+         |
+         | L0
+         |
+     SW 0 / USP0
+     SW 0 / DSP0
+         |
+         | L1
+         |
+        EP0
+
+In this example, there is a CXL switch between an endpoint and a root port.
+Latency in this example is calculated as such:
+L(EP0) - Latency from EP0 CDAT DSMAS+DSLBIS
+L(L1) - Link latency between EP0 and SW0DSP0
+L(SW0) - Latency for the switch from SW0 CDAT SSLBIS.
+L(L0) - Link latency between SW0 and RP0
+L(RP0) - Latency from root port to CPU via SRAT and HMAT (Generic Port).
+Total read and write latencies are the sum of all these parts.
+
+Bandwidth in this example is calculated as such:
+B(EP0) - Bandwidth from EP0 CDAT DSMAS+DSLBIS
+B(L1) - Link bandwidth between EP0 and SW0DSP0
+B(SW0) - Bandwidth for the switch from SW0 CDAT SSLBIS.
+B(L0) - Link bandwidth between SW0 and RP0
+B(RP0) - Bandwidth from root port to CPU via SRAT and HMAT (Generic Port).
+The total read and write bandwidth is the min() of all these parts.
+
+To calculate the link bandwidth:
+LinkOperatingFrequency (GT/s) is the current negotiated link speed.
+DataRatePerLink (MB/s) = LinkOperatingFrequency / 8
+Bandwidth (MB/s) = PCIeCurrentLinkWidth * DataRatePerLink
+Where PCIeCurrentLinkWidth is the number of lanes in the link.
+
+To calculate the link latency:
+LinkLatency (picoseconds) = FlitSize / LinkBandwidth (MB/s)
+
+See `CXL Memory Device SW Guide r1.0 <https://www.intel.com/content/www/us/en/content-details/643805/cxl-memory-device-software-guide.html>`_,
+section 2.11.3 and 2.11.4 for details.
+
+In the end, the access coordinates for a constructed memory region is calculated from one
+or more memory partitions from each of the CXL device(s).
+
 Shared Upstream Link Calculation
 ================================
 For certain CXL region construction with endpoints behind CXL switches (SW) or
@@ -90,3 +167,12 @@ under the same ACPI0017 device to form a new xarray.
 Finally, the cxl_region_update_bandwidth() is called and the aggregated
 bandwidth from all the members of the last xarray is updated for the
 access coordinates residing in the cxl region (cxlr) context.
+
+QTG ID
+======
+Each :doc:`CEDT <../platform/acpi/cedt>` has a QTG ID field. This field provides
+the ID that associates with a QoS Throttling Group (QTG) for the CFMWS window.
+Once the access coordinates are calculated, an ACPI Device Specific Method can
+be issued to the ACPI0016 device to retrieve the QTG ID depends on the access
+coordinates provided. The QTG ID for the device can be used as guidance to match
+to the CFMWS to setup the best Linux root decoder for the device performance.
-- 
2.49.0

Re: [PATCH v2 0/3] cxl: Update CXL documentation for access coordinates calculation

[Alison Schofield]

On Wed, May 14, 2025 at 05:09:20PM -0700, Dave Jiang wrote:
> v2:
> - Language clarifications (Gregory)
> - Move all CDAT bits into single document. (Gregory)
> - Define CDAT terms. (Gregory)
> 
> Add CXL access coordinates calculation documentation including CDAT details.

I appreciate this documentation and it makes me half-smart on this
stuff which leads to my possibly annoying questions:

Say I have a BIOS defined region. Can I look at the result of these
calcs and see, or judge, whether BIOS set up the most efficient
region?

For a user created region where the topology offers some flexibility,
can a user predict these numbers before creating a region? Can the
user create a region, evaluate its 'perf characteristics', then destroy
it and try another flavor?

I realize this is internal docs on driver behavior and not user
space documentation. I'm looking for info to improve my understanding
not suggesting this info belongs in these docs.

Thanks - and, for the series:

Reviewed-by: Alison Schofield <alison.schofield@intel.com>

> 
> 
> Dave Jiang (3):
>   cxl: docs/platform/cdat reference documentation
>   cxl: docs/platform/acpi/srat Add generic target documentation
>   cxl: doc/linux/access-coordinates Update access coordinates
>     calculation methods
> 
>  Documentation/driver-api/cxl/index.rst        |   1 +
>  .../cxl/linux/access-coordinates.rst          |  86 +++++++++++++
>  .../driver-api/cxl/platform/acpi/srat.rst     |  27 ++++
>  .../driver-api/cxl/platform/cdat.rst          | 118 ++++++++++++++++++
>  4 files changed, 232 insertions(+)
>  create mode 100644 Documentation/driver-api/cxl/platform/cdat.rst
> 
> 
> base-commit: 7855bc1362518673103bd9357827572207e6f6d9
> -- 
> 2.49.0
> 

Re: [PATCH v2 0/3] cxl: Update CXL documentation for access coordinates calculation

[Dave Jiang]

On 5/15/25 10:15 AM, Alison Schofield wrote:
> On Wed, May 14, 2025 at 05:09:20PM -0700, Dave Jiang wrote:
>> v2:
>> - Language clarifications (Gregory)
>> - Move all CDAT bits into single document. (Gregory)
>> - Define CDAT terms. (Gregory)
>>
>> Add CXL access coordinates calculation documentation including CDAT details.
> 
> I appreciate this documentation and it makes me half-smart on this
> stuff which leads to my possibly annoying questions:
> 
> Say I have a BIOS defined region. Can I look at the result of these
> calcs and see, or judge, whether BIOS set up the most efficient
> region?

Yes I think you can, since we do the calculation for all devices, not just the hot-plugged ones.

> 
> For a user created region where the topology offers some flexibility,
> can a user predict these numbers before creating a region? Can the
> user create a region, evaluate its 'perf characteristics', then destroy
> it and try another flavor?

I think so. If the QOS class mismatches, I believe you'll get a warning from CXL CLI, but you can override.

> 
> I realize this is internal docs on driver behavior and not user
> space documentation. I'm looking for info to improve my understanding
> not suggesting this info belongs in these docs.
> 
> Thanks - and, for the series:
> 
> Reviewed-by: Alison Schofield <alison.schofield@intel.com>
> 
>>
>>
>> Dave Jiang (3):
>>   cxl: docs/platform/cdat reference documentation
>>   cxl: docs/platform/acpi/srat Add generic target documentation
>>   cxl: doc/linux/access-coordinates Update access coordinates
>>     calculation methods
>>
>>  Documentation/driver-api/cxl/index.rst        |   1 +
>>  .../cxl/linux/access-coordinates.rst          |  86 +++++++++++++
>>  .../driver-api/cxl/platform/acpi/srat.rst     |  27 ++++
>>  .../driver-api/cxl/platform/cdat.rst          | 118 ++++++++++++++++++
>>  4 files changed, 232 insertions(+)
>>  create mode 100644 Documentation/driver-api/cxl/platform/cdat.rst
>>
>>
>> base-commit: 7855bc1362518673103bd9357827572207e6f6d9
>> -- 
>> 2.49.0
>>

Re: [PATCH v2 0/3] cxl: Update CXL documentation for access coordinates calculation

[Dave Jiang]

On 5/14/25 5:09 PM, Dave Jiang wrote:
> v2:
> - Language clarifications (Gregory)
> - Move all CDAT bits into single document. (Gregory)
> - Define CDAT terms. (Gregory)
> 
> Add CXL access coordinates calculation documentation including CDAT details.
> 
> 
> Dave Jiang (3):
>   cxl: docs/platform/cdat reference documentation
>   cxl: docs/platform/acpi/srat Add generic target documentation
>   cxl: doc/linux/access-coordinates Update access coordinates
>     calculation methods
> 
>  Documentation/driver-api/cxl/index.rst        |   1 +
>  .../cxl/linux/access-coordinates.rst          |  86 +++++++++++++
>  .../driver-api/cxl/platform/acpi/srat.rst     |  27 ++++
>  .../driver-api/cxl/platform/cdat.rst          | 118 ++++++++++++++++++
>  4 files changed, 232 insertions(+)
>  create mode 100644 Documentation/driver-api/cxl/platform/cdat.rst
> 
> 
> base-commit: 7855bc1362518673103bd9357827572207e6f6d9

Applied to cxl/next

Re: [PATCH v2 0/3] cxl: Update CXL documentation for access coordinates calculation

[Jonathan Cameron]

On Wed, 14 May 2025 17:09:20 -0700
Dave Jiang <dave.jiang@intel.com> wrote:

> v2:
> - Language clarifications (Gregory)
> - Move all CDAT bits into single document. (Gregory)
> - Define CDAT terms. (Gregory)

Obviously I'm late to the game, but fwiw I looked through this
and it looks good to me as well.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

> 
> Add CXL access coordinates calculation documentation including CDAT details.
> 
> 
> Dave Jiang (3):
>   cxl: docs/platform/cdat reference documentation
>   cxl: docs/platform/acpi/srat Add generic target documentation
>   cxl: doc/linux/access-coordinates Update access coordinates
>     calculation methods
> 
>  Documentation/driver-api/cxl/index.rst        |   1 +
>  .../cxl/linux/access-coordinates.rst          |  86 +++++++++++++
>  .../driver-api/cxl/platform/acpi/srat.rst     |  27 ++++
>  .../driver-api/cxl/platform/cdat.rst          | 118 ++++++++++++++++++
>  4 files changed, 232 insertions(+)
>  create mode 100644 Documentation/driver-api/cxl/platform/cdat.rst
> 
> 
> base-commit: 7855bc1362518673103bd9357827572207e6f6d9