public inbox for linux-cxl@vger.kernel.org
 help / color / mirror / Atom feed
From: Robert Richter <rrichter@amd.com>
To: Alison Schofield <alison.schofield@intel.com>,
	Vishal Verma <vishal.l.verma@intel.com>,
	Ira Weiny <ira.weiny@intel.com>,
	Dan Williams <dan.j.williams@intel.com>,
	Jonathan Cameron <Jonathan.Cameron@huawei.com>,
	Dave Jiang <dave.jiang@intel.com>,
	Davidlohr Bueso <dave@stgolabs.net>,
	Jonathan Cameron <jonathan.cameron@huawei.com>
Cc: <linux-cxl@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	Gregory Price <gourry@gourry.net>,
	"Fabio M. De Francesco" <fabio.m.de.francesco@linux.intel.com>,
	Terry Bowman <terry.bowman@amd.com>,
	Joshua Hahn <joshua.hahnjy@gmail.com>,
	Robert Richter <rrichter@amd.com>
Subject: [PATCH v4 12/14] cxl: Simplify cxl_rd_ops allocation and handling
Date: Mon, 3 Nov 2025 19:47:53 +0100	[thread overview]
Message-ID: <20251103184804.509762-13-rrichter@amd.com> (raw)
In-Reply-To: <20251103184804.509762-1-rrichter@amd.com>

A root decoder's callback handlers are collected in struct cxl_rd_ops.
The structure is dynamically allocated, though it contains only a few
pointers in it. This also requires to check two pointes to check for
the existance of a callback.

Simplify the allocation, release and handler check by embedding the
ops statical in struct cxl_root_decoder.

Implementation is equivalent to how struct cxl_root_ops handles the
callbacks.

Signed-off-by: Robert Richter <rrichter@amd.com>
---
 drivers/cxl/acpi.c        |  8 ++------
 drivers/cxl/core/region.c | 20 +++++---------------
 drivers/cxl/cxl.h         |  2 +-
 3 files changed, 8 insertions(+), 22 deletions(-)

diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c
index f9bbc77f3ec2..778ee29430ea 100644
--- a/drivers/cxl/acpi.c
+++ b/drivers/cxl/acpi.c
@@ -471,12 +471,8 @@ static int __cxl_parse_cfmws(struct acpi_cedt_cfmws *cfmws,
 	cxlrd->qos_class = cfmws->qtg_id;
 
 	if (cfmws->interleave_arithmetic == ACPI_CEDT_CFMWS_ARITHMETIC_XOR) {
-		cxlrd->ops = kzalloc(sizeof(*cxlrd->ops), GFP_KERNEL);
-		if (!cxlrd->ops)
-			return -ENOMEM;
-
-		cxlrd->ops->hpa_to_spa = cxl_apply_xor_maps;
-		cxlrd->ops->spa_to_hpa = cxl_apply_xor_maps;
+		cxlrd->ops.hpa_to_spa = cxl_apply_xor_maps;
+		cxlrd->ops.spa_to_hpa = cxl_apply_xor_maps;
 	}
 
 	rc = cxl_decoder_add(cxld);
diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
index 379a67cc8e31..dec003084521 100644
--- a/drivers/cxl/core/region.c
+++ b/drivers/cxl/core/region.c
@@ -2932,16 +2932,6 @@ static bool cxl_is_hpa_in_chunk(u64 hpa, struct cxl_region *cxlr, int pos)
 	return false;
 }
 
-static bool has_hpa_to_spa(struct cxl_root_decoder *cxlrd)
-{
-	return cxlrd->ops && cxlrd->ops->hpa_to_spa;
-}
-
-static bool has_spa_to_hpa(struct cxl_root_decoder *cxlrd)
-{
-	return cxlrd->ops && cxlrd->ops->spa_to_hpa;
-}
-
 u64 cxl_dpa_to_hpa(struct cxl_region *cxlr, const struct cxl_memdev *cxlmd,
 		   u64 dpa)
 {
@@ -2996,8 +2986,8 @@ u64 cxl_dpa_to_hpa(struct cxl_region *cxlr, const struct cxl_memdev *cxlmd,
 	hpa = hpa_offset + p->res->start + p->cache_size;
 
 	/* Root decoder translation overrides typical modulo decode */
-	if (has_hpa_to_spa(cxlrd))
-		hpa = cxlrd->ops->hpa_to_spa(cxlrd, hpa);
+	if (cxlrd->ops.hpa_to_spa)
+		hpa = cxlrd->ops.hpa_to_spa(cxlrd, hpa);
 
 	if (!cxl_resource_contains_addr(p->res, hpa)) {
 		dev_dbg(&cxlr->dev,
@@ -3006,7 +2996,7 @@ u64 cxl_dpa_to_hpa(struct cxl_region *cxlr, const struct cxl_memdev *cxlmd,
 	}
 
 	/* Simple chunk check, by pos & gran, only applies to modulo decodes */
-	if (!has_hpa_to_spa(cxlrd) && (!cxl_is_hpa_in_chunk(hpa, cxlr, pos)))
+	if (!cxlrd->ops.hpa_to_spa && !cxl_is_hpa_in_chunk(hpa, cxlr, pos))
 		return ULLONG_MAX;
 
 	return hpa;
@@ -3041,8 +3031,8 @@ static int region_offset_to_dpa_result(struct cxl_region *cxlr, u64 offset,
 	 * If the root decoder has SPA to CXL HPA callback, use it. Otherwise
 	 * CXL HPA is assumed to equal SPA.
 	 */
-	if (has_spa_to_hpa(cxlrd)) {
-		hpa = cxlrd->ops->spa_to_hpa(cxlrd, p->res->start + offset);
+	if (cxlrd->ops.spa_to_hpa) {
+		hpa = cxlrd->ops.spa_to_hpa(cxlrd, p->res->start + offset);
 		hpa_offset = hpa - p->res->start;
 	} else {
 		hpa_offset = offset;
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 0af46d1b0abc..75fd45ddca38 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -451,7 +451,7 @@ struct cxl_root_decoder {
 	void *platform_data;
 	struct mutex range_lock;
 	int qos_class;
-	struct cxl_rd_ops *ops;
+	struct cxl_rd_ops ops;
 	struct cxl_switch_decoder cxlsd;
 };
 
-- 
2.47.3


  parent reply	other threads:[~2025-11-03 18:49 UTC|newest]

Thread overview: 66+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-03 18:47 [PATCH v4 00/14] cxl: ACPI PRM Address Translation Support and AMD Zen5 enablement Robert Richter
2025-11-03 18:47 ` [PATCH v4 01/14] cxl/region: Store root decoder in struct cxl_region Robert Richter
2025-11-11 14:45   ` Jonathan Cameron
2025-11-14  9:38     ` Robert Richter
2025-11-03 18:47 ` [PATCH v4 02/14] cxl/region: Store HPA range " Robert Richter
2025-11-11 11:25   ` Robert Richter
2025-11-03 18:47 ` [PATCH v4 03/14] cxl/region: Rename misleading variable name @hpa to @hpa_range Robert Richter
2025-11-03 21:36   ` Dave Jiang
2025-11-11 14:41   ` Jonathan Cameron
2025-11-12 16:23     ` Dave Jiang
2025-11-03 18:47 ` [PATCH v4 04/14] cxl/region: Add @hpa_range argument to function cxl_calc_interleave_pos() Robert Richter
2025-11-03 21:52   ` Dave Jiang
2025-11-04  3:04   ` Alison Schofield
2025-11-11 11:28     ` Robert Richter
2025-11-04 16:52   ` kernel test robot
2025-11-03 18:47 ` [PATCH v4 05/14] cxl: Simplify cxl_root_ops allocation and handling Robert Richter
2025-11-03 21:53   ` Dave Jiang
2025-11-04 23:02     ` Dave Jiang
2025-11-07 15:45       ` Robert Richter
2025-11-07 15:50         ` Dave Jiang
2025-11-11 14:52   ` Jonathan Cameron
2025-11-03 18:47 ` [PATCH v4 06/14] cxl/region: Separate region parameter setup and region construction Robert Richter
2025-11-03 22:05   ` Dave Jiang
2025-11-07 15:59     ` Robert Richter
2025-11-11 14:59       ` Jonathan Cameron
2025-11-11 15:02   ` Jonathan Cameron
2025-11-03 18:47 ` [PATCH v4 07/14] cxl/region: Use region data to get the root decoder Robert Richter
2025-11-03 22:30   ` Dave Jiang
2025-11-11 15:14   ` Jonathan Cameron
2025-11-03 18:47 ` [PATCH v4 08/14] cxl: Introduce callback for HPA address ranges translation Robert Richter
2025-11-03 23:09   ` Dave Jiang
2025-11-11 15:15   ` Jonathan Cameron
2025-11-03 18:47 ` [PATCH v4 09/14] cxl/acpi: Prepare use of EFI runtime services Robert Richter
2025-11-03 23:34   ` Dave Jiang
2025-11-11 15:17   ` Jonathan Cameron
2025-11-03 18:47 ` [PATCH v4 10/14] cxl: Enable AMD Zen5 address translation using ACPI PRMT Robert Richter
2025-11-04  1:00   ` Dave Jiang
2025-11-11  9:23     ` Robert Richter
2025-11-04  9:33   ` kernel test robot
2025-11-04 12:49     ` Robert Richter
2025-11-04 23:35   ` kernel test robot
2025-11-11 15:30   ` Jonathan Cameron
2025-11-13 11:24     ` Robert Richter
2025-11-03 18:47 ` [PATCH v4 11/14] cxl/atl: Lock decoders that need address translation Robert Richter
2025-11-04 17:13   ` Dave Jiang
2025-11-11 12:54     ` Robert Richter
2025-11-12 16:34       ` Dave Jiang
2025-11-13 20:05         ` Robert Richter
2025-11-13 20:36           ` Dave Jiang
2025-11-14  7:34             ` Robert Richter
2025-11-14 15:21               ` Dave Jiang
2025-11-11 15:31   ` Jonathan Cameron
2025-11-03 18:47 ` Robert Richter [this message]
2025-11-04 17:26   ` [PATCH v4 12/14] cxl: Simplify cxl_rd_ops allocation and handling Dave Jiang
2025-11-04 23:02   ` Alison Schofield
2025-11-11 12:07     ` Robert Richter
2025-11-11 15:34   ` Jonathan Cameron
2025-11-03 18:47 ` [PATCH v4 13/14] cxl/acpi: Group xor arithmetric setup code in a single block Robert Richter
2025-11-11 15:35   ` Jonathan Cameron
2025-11-03 18:47 ` [PATCH v4 14/14] cxl/region: Remove local variable @inc in cxl_port_setup_targets() Robert Richter
2025-11-11 15:36   ` Jonathan Cameron
2025-11-13 20:10     ` Robert Richter
2025-11-04 16:17 ` [PATCH v4 00/14] cxl: ACPI PRM Address Translation Support and AMD Zen5 enablement Alison Schofield
2025-11-17 15:34   ` Robert Richter
2025-11-17 17:23     ` Gregory Price
2025-11-11 14:01 ` Gregory Price

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20251103184804.509762-13-rrichter@amd.com \
    --to=rrichter@amd.com \
    --cc=Jonathan.Cameron@huawei.com \
    --cc=alison.schofield@intel.com \
    --cc=dan.j.williams@intel.com \
    --cc=dave.jiang@intel.com \
    --cc=dave@stgolabs.net \
    --cc=fabio.m.de.francesco@linux.intel.com \
    --cc=gourry@gourry.net \
    --cc=ira.weiny@intel.com \
    --cc=joshua.hahnjy@gmail.com \
    --cc=linux-cxl@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=terry.bowman@amd.com \
    --cc=vishal.l.verma@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox