Re: RFC: CXL Isolation Support

[Jonathan Cameron <jonathan.cameron@huawei.com>]

> Possible Solutions
> ------------------
> There's a couple of things we could do here. First is to restrict isolation to when
> the CXL core is built-in (CXL_BUS=y && depends on PCIEPORTBUS). I'm not particularly
> happy about this approach since it removes the modularity of the CXL driver(s), but I
> won't gripe if that's what's settled on.

It's the sort of constraint we can relax later if that becomes possible.

> 
> Another approach would be to move the CXL register mapping code in cxl/core/regs.c to a
> library, or always make the file built-in when CXL_BUS is selected. This is more palatable
> (imo) but splits the CXL code up in a potentially weird way.
> 
> Last one is to rework the PCIe port bus driver to allow for re-allocating MSI/-X interrupts.
> Jonathan Cameron sent out a series where there was some discussion on this. This support
> would be limited to MSI-X interrupts only due to the PCI maintainers not wanting to add
> more support for MSI [4].

> This wouldn't work for AMD platforms because we use MSI interrupts
> for this support. There is still a way to make this work, however. AMD server platforms
> use the same MSI vector for all PCIe interrupts, so we could introduce a quirk to use that
> same vector as another PCIe interrupt for CXL isolation. That would require no register mapping
> code in the PCIe portdrv code but would introduce a platform quirk instead. I doubt anyone would
> be happy about introducing a quirk but I thought I'd throw it out as an option.

That whole approach (I failed to follow up so far) in [4] never took shared interrupts into account.
So might well have been quirk territory even with that rework done (with MSI as a possible
controversial follow up to the MSI-X version).

Jonathan



> 
> Thanks for reading,
> Ben

>