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From: Richard Cheng <icheng@nvidia.com>
To: dave@stgolabs.net, jic23@kernel.org, dave.jiang@intel.com,
	alison.schofield@intel.com, vishal.l.verma@intel.com,
	ira.weiny@intel.com, djbw@kernel.org
Cc: terry.bowman@amd.com, gourry@gourry.net, ming.li@zohomail.com,
	alucerop@amd.com, linux-cxl@vger.kernel.org,
	linux-kernel@vger.kernel.org, newtonl@nvidia.com,
	kristinc@nvidia.com, kaihengf@nvidia.com, kobak@nvidia.com,
	vaslot@nvidia.com, smadhavan@nvidia.com,
	Richard Cheng <icheng@nvidia.com>
Subject: [PATCH 1/2] cxl: Convert PCIBIOS errors to errno on remaining DVSEC/PCIe accesses
Date: Sun,  7 Jun 2026 15:02:40 +0800	[thread overview]
Message-ID: <20260607070241.48978-2-icheng@nvidia.com> (raw)
In-Reply-To: <20260607070241.48978-1-icheng@nvidia.com>

PCI config and PCIe capability accessors return positive PCIBIOS_*
status codes on failure, not negative errnos. update_gpf_port_dvsec()
and cxl_setup_parent_dport() propagate these raw values to callers that
test for failure with "if (rc)" and expect a negative errno, which can
misreport the error.

Conver the positive PCIBIOS status with pcibios_err_to_errno() on these
error paths.

Signed-off-by: Richard Cheng <icheng@nvidia.com>
---
 drivers/cxl/core/pci.c | 2 +-
 drivers/cxl/port.c     | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index e4338fd7e01b..ea81a170132f 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -852,7 +852,7 @@ static int update_gpf_port_dvsec(struct pci_dev *pdev, int dvsec, int phase)
 		pci_dbg(pdev, "Port GPF phase %d timeout: %d0 secs\n",
 			phase, GPF_TIMEOUT_BASE_MAX);
 
-	return rc;
+	return pcibios_err_to_errno(rc);
 }
 
 int cxl_gpf_port_setup(struct cxl_dport *dport)
diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
index ada51948d52f..dc3029efb087 100644
--- a/drivers/cxl/port.c
+++ b/drivers/cxl/port.c
@@ -92,7 +92,7 @@ static int cxl_ras_unmask(struct cxl_port *port)
 
 	rc = pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap);
 	if (rc)
-		return rc;
+		return pcibios_err_to_errno(rc);
 
 	if (cap & PCI_EXP_DEVCTL_URRE) {
 		addr = port->regs.ras + CXL_RAS_UNCORRECTABLE_MASK_OFFSET;
-- 
2.43.0


  reply	other threads:[~2026-06-07  7:03 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-07  7:02 [PATCH 0/2] cxl: Convert remaining PCIBIOS errors to errno Richard Cheng
2026-06-07  7:02 ` Richard Cheng [this message]
2026-06-07  7:13   ` [PATCH 1/2] cxl: Convert PCIBIOS errors to errno on remaining DVSEC/PCIe accesses sashiko-bot
2026-06-07  7:02 ` [PATCH 2/2] cxl/core/regs: Check return value of DVSEC register locator reads Richard Cheng
2026-06-07  7:13   ` sashiko-bot

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