Linux CXL
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From: Richard Cheng <icheng@nvidia.com>
To: dave@stgolabs.net, jic23@kernel.org, dave.jiang@intel.com,
	alison.schofield@intel.com, vishal.l.verma@intel.com,
	ira.weiny@intel.com, djbw@kernel.org
Cc: terry.bowman@amd.com, gourry@gourry.net, ming.li@zohomail.com,
	alucerop@amd.com, linux-cxl@vger.kernel.org,
	linux-kernel@vger.kernel.org, newtonl@nvidia.com,
	kristinc@nvidia.com, kaihengf@nvidia.com, kobak@nvidia.com,
	vaslot@nvidia.com, smadhavan@nvidia.com,
	Richard Cheng <icheng@nvidia.com>
Subject: [PATCH 2/2] cxl/core/regs: Check return value of DVSEC register locator reads
Date: Sun,  7 Jun 2026 15:02:41 +0800	[thread overview]
Message-ID: <20260607070241.48978-3-icheng@nvidia.com> (raw)
In-Reply-To: <20260607070241.48978-1-icheng@nvidia.com>

__cxl_find_regblock_instance() reads the CXL Register Locator DVSEC via
pci_read_config_dword() but ignores the return value. On a failed config
read the raw accessor leaves PCI_ERROR_RESPONSE (~0) in the destination,
so the code computes a huge regblock count and decodes register block
addresses from garbage instead of detecting the failure.

Check the return value and convert the positive PCIBIOS_* status to a
negative errno with pcibios_err_to_errno() on the error paths.

Fixes: 303ebc1b1741 ("cxl/acpi: Map component registers for Root Ports")
Signed-off-by: Richard Cheng <icheng@nvidia.com>
---
 drivers/cxl/core/regs.c | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
index 93710cf4f0a6..bbb1c278c4d8 100644
--- a/drivers/cxl/core/regs.c
+++ b/drivers/cxl/core/regs.c
@@ -303,7 +303,7 @@ static int __cxl_find_regblock_instance(struct pci_dev *pdev, enum cxl_regloc_ty
 {
 	u32 regloc_size, regblocks;
 	int instance = 0;
-	int regloc, i;
+	int regloc, i, rc;
 
 	*map = (struct cxl_register_map) {
 		.host = &pdev->dev,
@@ -315,7 +315,9 @@ static int __cxl_find_regblock_instance(struct pci_dev *pdev, enum cxl_regloc_ty
 	if (!regloc)
 		return -ENXIO;
 
-	pci_read_config_dword(pdev, regloc + PCI_DVSEC_HEADER1, &regloc_size);
+	rc = pci_read_config_dword(pdev, regloc + PCI_DVSEC_HEADER1, &regloc_size);
+	if (rc)
+		return pcibios_err_to_errno(rc);
 	regloc_size = PCI_DVSEC_HEADER1_LEN(regloc_size);
 
 	regloc += PCI_DVSEC_CXL_REG_LOCATOR_BLOCK1;
@@ -324,8 +326,12 @@ static int __cxl_find_regblock_instance(struct pci_dev *pdev, enum cxl_regloc_ty
 	for (i = 0; i < regblocks; i++, regloc += 8) {
 		u32 reg_lo, reg_hi;
 
-		pci_read_config_dword(pdev, regloc, &reg_lo);
-		pci_read_config_dword(pdev, regloc + 4, &reg_hi);
+		rc = pci_read_config_dword(pdev, regloc, &reg_lo);
+		if (rc)
+			return pcibios_err_to_errno(rc);
+		rc = pci_read_config_dword(pdev, regloc + 4, &reg_hi);
+		if (rc)
+			return pcibios_err_to_errno(rc);
 
 		if (!cxl_decode_regblock(pdev, reg_lo, reg_hi, map))
 			continue;
-- 
2.43.0


  parent reply	other threads:[~2026-06-07  7:03 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-07  7:02 [PATCH 0/2] cxl: Convert remaining PCIBIOS errors to errno Richard Cheng
2026-06-07  7:02 ` [PATCH 1/2] cxl: Convert PCIBIOS errors to errno on remaining DVSEC/PCIe accesses Richard Cheng
2026-06-07  7:13   ` sashiko-bot
2026-06-07  7:02 ` Richard Cheng [this message]
2026-06-07  7:13   ` [PATCH 2/2] cxl/core/regs: Check return value of DVSEC register locator reads sashiko-bot

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