From: sashiko-bot@kernel.org
To: "Alison Schofield" <alison.schofield@intel.com>
Cc: linux-cxl@vger.kernel.org
Subject: Re: [PATCH v2 4/6] cxl/region: Validate mixed-granularity at sysfs and attach gates
Date: Thu, 11 Jun 2026 18:03:33 +0000 [thread overview]
Message-ID: <20260611180334.7EC6B1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <42da0b69d39207b712d7c27f1af6186febbeaa6f.1781199122.git.alison.schofield@intel.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
Pre-existing issues:
- [High] The function `check_interleave_cap()` ignores the return values of `ways_to_eiw()` and `granularity_to_eig()`, leading to the use of uninitialized stack variables (`eiw`, `eig`) in bitmask calculations.
--
commit 999caa321a85ce92543a94c3525b252f33aab308
Author: Alison Schofield <alison.schofield@intel.com>
cxl/region: Validate mixed-granularity at sysfs and attach gates
Replace the same-granularity sysfs check with is_ig_allowed() to permit valid
mixed-granularity regions. Call this helper at attach time to enforce the same
rules for auto regions, and add an explicit span equality check for
3-way-family roots.
> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> index 9fff538a9ce16..311b5052bbc8f 100644
> --- a/drivers/cxl/core/region.c
> +++ b/drivers/cxl/core/region.c
[ ... ]
> @@ -2096,6 +2107,8 @@ static int cxl_region_attach(struct cxl_region *cxlr,
> struct cxl_dport *dport;
> int rc = -ENXIO;
> int stride;
> + int root_ways = cxlrd->cxlsd.cxld.interleave_ways;
> + int root_gran = cxlrd->cxlsd.cxld.interleave_granularity;
>
> rc = check_interleave_cap(&cxled->cxld, p->interleave_ways,
> p->interleave_granularity);
[Severity: High]
This isn't a bug introduced by this patch, but check_interleave_cap() is
called here with potentially uninitialized (zero) values for interleave_ways
and interleave_granularity prior to state verification.
Inside check_interleave_cap() in drivers/cxl/core/region.c, ways_to_eiw() and
granularity_to_eig() are called but their return values are ignored:
ways_to_eiw(iw, &eiw);
if (eiw == 0 || eiw == 8)
return 0;
granularity_to_eig(ig, &eig);
if (eiw > 8)
high_pos = eiw + eig - 1;
else
high_pos = eiw + eig + 7;
low_pos = eig + 8;
interleave_mask = GENMASK(high_pos, low_pos);
If interleave_ways and interleave_granularity are 0, both ways_to_eiw() and
granularity_to_eig() return -EINVAL, leaving eiw and eig uninitialized.
Because eig is an uninitialized u16, low_pos can be as large as 65543.
Passing values greater than 64 to GENMASK() results in an out-of-bounds
bitwise shift.
On systems with CONFIG_UBSAN_TRAP enabled, could this lead to a kernel panic
if a privileged user misorders sysfs writes?
--
Sashiko AI review · https://sashiko.dev/#/patchset/cover.1781199122.git.alison.schofield@intel.com?part=4
next prev parent reply other threads:[~2026-06-11 18:03 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-11 17:47 [PATCH v2 0/6] cxl: Support mixed-granularity region interleaves Alison Schofield
2026-06-11 17:47 ` [PATCH v2 1/6] cxl/region: Validate interleave selector bits Alison Schofield
2026-06-11 17:47 ` [PATCH v2 2/6] cxl/region: Derive port granularity from " Alison Schofield
2026-06-11 17:47 ` [PATCH v2 3/6] cxl/region: Account for mixed-granularity in position calculations Alison Schofield
2026-06-11 18:01 ` sashiko-bot
2026-06-12 6:21 ` Richard Cheng
2026-06-11 17:47 ` [PATCH v2 4/6] cxl/region: Validate mixed-granularity at sysfs and attach gates Alison Schofield
2026-06-11 18:03 ` sashiko-bot [this message]
2026-06-11 17:47 ` [PATCH v2 5/6] cxl/test: Add a topology to test mixed-granularity regions Alison Schofield
2026-06-11 17:47 ` [PATCH v2 6/6] Documentation/cxl: Add region granularity and multi-level interleave guide Alison Schofield
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