[PATCH v2 0/6] cxl: Support mixed-granularity region interleaves

[Alison Schofield <alison.schofield@intel.com>]

Changes in v2:
- Patch 1,2: Defer the unused selector var store to keep P1 bisectable (Sashiko)
- Patch 1: Make divide by 3 in get_selctor() work on 32-bit builds) (lkp)
- Patch 4: Use local vars in cxl_region_attach() for readability (DaveJ)
- Patch 5: Add NULL checks on unused mock arrays (Sashiko)
- Resolved errant err_rch unwind with rc7 merge (DaveJ)
- Rebase onto 7.1-rc7
- Update commit logs in 1,2,5 to align w changes in v2 
Link to v1:
https://lore.kernel.org/all/cover.1780095671.git.alison.schofield@intel.com/

Begin Cover Letter:

A CXL region interleaves across decoder levels (root, optional
switches, endpoint). CXL Spec 4.0 Section 9.13.1 requires only
that each level use a different, consecutive range of HPA bits to
select its target. The driver has historically required equal
region and root decoder granularities. That blocks the legal
mixed-granularity arrangements permitted by Section 9.13.1, and
makes the 6-way and 12-way configurations defined in Section
9.13.1.1 (Tables 9-6, 9-7, and 9-8) impossible to create.

Two prior proposals addressed parts of this gap:

AlisonS added position arithmetic and sysfs gating to allow
auto and user-created regions for the 6-way and 12-way
configurations that have no same-granularity alternative:
https://lore.kernel.org/all/20250306232239.2609017-1-alison.schofield@intel.com/

RobertR introduced an HPA selector-bit model to allow multi-level
regions regardless of granularity ordering for auto regions:
https://lore.kernel.org/all/20251028094754.72816-1-rrichter@amd.com/

This series combines those two approaches into a complete mixed-
granularity implementation. It extends Robert's selector-bit model
from auto regions to user-created regions, extends AlisonS's
position-arithmetic and gating work to all mixed-gran layouts, and
adds the remaining validation needed for both paths. The result is
support for every mixed-granularity arrangement defined by the CXL
specification.


Series structure
----------------
Patches 1 and 2 replace the old granularity ordering rule with
selector-bit validation. Patches 3 and 4 propagate that model through
the remaining region-creation paths. Patch 5 adds cxl_test coverage
for the new layouts. Patch 6 documents the region granularity model
and multi-level interleaving rules.

A companion NDCTL patchset that allows mixed-gran 'cxl create-region'
and adds the unit test is posted here:
https://lore.kernel.org/all/fa5c109f08824180f58341ebd9055545a2ff3142.1780099216.git.alison.schofield@intel.com/

Alison Schofield (6):
  cxl/region: Validate interleave selector bits
  cxl/region: Derive port granularity from selector bits
  cxl/region: Account for mixed-granularity in position calculations
  cxl/region: Validate mixed-granularity at sysfs and attach gates
  cxl/test: Add a topology to test mixed-granularity regions
  Documentation/cxl: Add region granularity and multi-level interleave
    guide

 Documentation/driver-api/cxl/index.rst        |   1 +
 .../cxl/linux/region-granularity.rst          | 486 +++++++++++++++++
 drivers/cxl/core/region.c                     | 312 +++++++----
 tools/testing/cxl/test/cxl.c                  | 503 ++++++++++++++++--
 4 files changed, 1159 insertions(+), 143 deletions(-)
 create mode 100644 Documentation/driver-api/cxl/linux/region-granularity.rst


base-commit: 4549871118cf616eecdd2d939f78e3b9e1dddc48
-- 
2.37.3